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R. K. Kavitha

Observed names: R K Kavitha, R Kavitha, R. Kavitha, R.K. Kavitha
ORCID: 0000-0002-2480-0876
Observed ORCID: 0000-0002-2480-0876
OpenAlex ID: A5100630280
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic
2012 · Kalarikkal Absel, Lijo Manuel, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 68
Low-Power Dual-Vt 7T SRAM Bit-Cell With Reduced Area and Leakage
2022 · Sheethal Yadav, Yash Bansal, et al. · IEEE Delhi Section Conference (DELCON) · 8
Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors
2025 · Biby Joseph, R.K. Kavitha · Microelectronics Reliability · 6
Energy Efficient Memory Decoder for SRAM Based AI Accelerator
2023 · Biby Joseph, Gopireddy Chaithanyakumar Reddy, et al. · International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS) · 6
Design of a robust method to acquire EOG signals using Bio-medical signal processing
2016 · Suraj Kiran Raman, Jayadev Kumar Jayaram, et al. · Online International Conference on Green Engineering and Technologies · 6
High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style
2013 · C. K. Midhun, Jephy Joy, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 6
A Compact 2T1C and Cryo-2T1C CMOS Memristor Emulator for Neuromorphic and Quantum Computing
2025 · Sara Paul, Digambar Laxman Bhole, et al. · AEU - International Journal of Electronics and Communications · 5
A radiation hardened In-memory computing SRAM for soft error tolerance in safety critical applications
2025 · Biby Joseph, R.K. Kavitha · AEU - International Journal of Electronics and Communications · 4
High-performance asynchronous pipeline using embedded delay element
2019 · R.K. Kavitha, A. Khajamastan, et al. · Microprocessors and Microsystems · 4
A 4T1C Cryogenic Inverse CMOS Memristor Emulator For Quantum Computing Application
2025 · Sara Paul, R.K. Kavitha · AEU - International Journal of Electronics and Communications · 3
Dual Vt 7T SRAM Based In-Memory Compute Adder for Convolution Neural Network Applications
2023 · Biby Joseph, R. K. Kavitha · International Conference for Innovation in Technology (INOCON) · 2
High Speed Synchronization Using Modified Pausible Clocking Method
2019 · R K Kavitha, P R Rahul, et al. · IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 1
Low Power Data Driven Conditional Precharge Dynamic Flip Flop
2017 · R. K. Kavitha, Vineeth Johns Toms, et al. · Journal of Low Power Electronics · 1
A Mathematical Model of TiO2 Memristor Without Control Parameters
2024 · Sara Paul, R. K. Kavitha · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
Design and Analysis of Multiplexer Based D-Flip Flop Using QCA Implementation
2021 · Allam Naveen, C. V. Priyanka, et al. · Lecture notes in electrical engineering
An Efficient Approach for Test Pattern Generation in Scan Based BIST
2017 · R Kavitha, R Vishnupriya · International Journal of Industrial Engineering
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Sub-1V ultra low-power voltage reference
2015 · C Mohammed Abbas, Abhishek Shukla, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
Healthcare Measurement of ECG and Body Temperature Signals Using Android Mobile
2014 · V. Navaneethan, R. Kavitha · Asian Journal of Engineering and Applied Technology
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Low power consumption of sequential circuit of digital ICS
2014 · T. D. Subash, T. Gnanasekaran, et al. · International Conference on Devices, Circuits and Systems (ICDCS)
High speed dynamic asynchronous pipeline: Self-Controlled approach
2012 · L. Manuel, C. K. Midhun, et al. · IEEE India Conference
Secured and Authenticated Communication in Cloud Using Dynamic Key Exchange Protocol
2012 · J. V. Anchitaalagammai, R. K. Kavitha, et al.
Works count: 21
Citation count: 120
H-index: 6
I10-index: 1
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