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Yan Lin
Observed name:
Lin Yan
Institutions:
ByteDance (China),
Chengyi College, Jimei University
Observed institutions:
University of California, Los Angeles,
China Academy of Space Technology,
ByteDance (China),
Chengyi College, Jimei University
ORCID:
0009-0001-4169-6150
Observed ORCID:
0009-0001-4169-6150
OpenAlex ID:
A5101026950
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
2004
·
Fei Li
, Yan Lin
, et al.
·
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
·
157
FPGA power reduction using configurable dual-Vdd
2004
·
Fei Li
, Yan Lin
, et al.
·
Proceedings - ACM IEEE Design Automation Conference
·
96
Vdd programmability to reduce FPGA interconnect power
2005
·
Fei Li
, Yan Lin
, et al.
·
71
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
2005
·
Yan Lin
, Fei Li
, et al.
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
·
49
FPGA device and architecture evaluation considering process variations
2005
·
Ho-Yan Wong
, Lerong Cheng
, et al.
·
48
Placement and Timing for FPGAs Considering Variations
2006
·
Yan Lin
, Mike Hutton
, et al.
·
International Conference on Field Programmable Logic and Applications (FPL)
·
39
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
2005
·
Yan Lin
, Fei Li
, et al.
·
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
·
31
Field Programmability of Supply Voltages for FPGA Power Reduction
2007
·
Fei Li
, Yan Lin
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
29
Device and architecture co-optimization for FPGA power reduction
2005
·
Lerong Cheng
, Phoebe Wong
, et al.
·
Proceedings - ACM IEEE Design Automation Conference
·
22
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
2005
·
Yan Lin
, Lei He
·
Proceedings - ACM IEEE Design Automation Conference
·
21
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
2006
·
Yu Hu
, Yan Lin
, et al.
·
Proceedings - ACM IEEE Design Automation Conference
·
20
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs
2008
·
Yan Lin
, Lei He
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
18
Device and Architecture Cooptimization for FPGA Power Reduction
2007
·
Lerong Cheng
, Fei Li
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
16
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation
2007
·
Yan Lin
, Lei He
·
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
·
14
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
2008
·
Yu Hu
, Yan Lin
, et al.
·
ACM Transactions on Design Automation of Electronic Systems
·
12
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
2005
·
Yan Lin
, Fei Li
, et al.
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
·
11
Device and architecture concurrent optimization for FPGA transient soft error rate
2007
·
Yan Lin
, Lei He
·
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
·
10
Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction
2007
·
Yan Lin
, Lei He
·
Design, Automation, and Test in Europe
·
9
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability
2008
·
Lerong Cheng
, Yan Lin
, et al.
·
8
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
2006
·
Yan Lin
, Yu Hu
, et al.
·
International Symposium on Low Power Electronics and Design (ISLPED)
·
4
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
2012
·
Lerong Cheng
, Wenyao Xu
, et al.
·
ACM Transactions on Reconfigurable Technology and Systems
·
2
Flaming-hot Initiation with Regular Execution Sampling for Large Language Models
2025
·
Weizhe Chen
, Zhicheng Zhang
, et al.
·
Findings of the Association for Computational Linguistics: NAACL
·
1
PDF
Design Method of Product Agile Customization Based on Artificial Neural Network and Its Application
2011
·
Changfeng Yuan
, Wanlei Wang
, et al.
·
Journal of Computers
·
1
Talking about Equipment Management and Its Development Direction
2010
·
Yan Lin
·
Sci-Tech Information Development & Economy
·
1
Compare of the reliability standards used for space electronic products in ECSS and CAST
2009
·
Li Li
, Cheng'an Wan
, et al.
·
International Conference on Reliability, Maintainability and Safety
·
1
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Works count:
29
Citation count:
692
H-index:
14
I10-index:
17
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