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D.M. Wu

Observed names: D. M. Wu, D. Wu, Diancheng Wu, Ding Wu, Dingcheng Wu, Dong-Lin Wu
Observed institutions: Florida Institute of Technology, University of Science and Technology of China, IBM (United States), Intel (United States), National Sun Yat-sen University, Nanyang Technological University, Chinese Academy of Sciences, Center for Excellence in Brain Science and Intelligence Technology, Institute of Geodesy and Geophysics, AviChina Industry & Technology (China), IBM Research - Austin, University of Chinese Academy of Sciences, State Key Laboratory of Geodesy and Earth's Dynamics, State Key Laboratory of Neuroscience
ORCID: 0000-0002-3591-7754
Observed ORCID: 0000-0002-3591-7754
OpenAlex ID: A5101720948
Groundwater Depletion in the West Liaohe River Basin, China and Its Implications Revealed by GRACE and In Situ Measurements
2018 · Yulong Zhong, Min Zhong, et al. · Remote Sensing · 121
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Cold delay defect screening
2002 · Chao-Wen Tseng, E.J. Mccluskey, et al. · IEEE VLSI Test Symposium (VTS) · 43
TSAnalyzer, a GNSS time series analysis software
2017 · Dingcheng Wu, Haoming Yan, et al. · GPS Solutions · 41
L1 regularization for detecting offsets and trend change points in GNSS time series
2018 · Dingcheng Wu, Haoming Yan, et al. · GPS Solutions · 38
Evolution and Neural Representation of Mammalian Cooperative Behavior
2021 · Mengping Jiang, Miaoyaoxin Wang, et al. · Cell Reports · 33
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An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor
2005 · D.M. Wu, M. Lin, et al. · 16
II-DFT: a hybrid dft architecture for low-cost high quality structural testing
2004 · D.M. Wu, M. Lin, et al. · IEEE International Test Conference (ITC) · 14
Defect analysis, test generation and fault simulation for gate oxide shorts in CMOS ICs
2002 · S.I. Syed, D.M. Wu · IEEE International Symposium on Circuits and Systems proceedings · 12
Applying Reconstructed Daily Water Storage and Modified Wetness Index to Flood Monitoring: A Case Study in the Yangtze River Basin
2023 · Cuiyu Xiao, Yulong Zhong, et al. · Remote Sensing · 11
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Test generation for VLSI chips with embedded memories
1990 · E. K. Vida-Torku, J. A. Monzel, et al. · IBM Journal of Research and Development · 10
Full-Reference Image Quality Assessment via Low-Level and High-Level Feature Fusion
2023 · Chao Wu, Xiaofeng Liao, et al. · International Journal of Pattern Recognition and Artificial Intelligence · 6
Built-in test using perturbed deterministic patterns
2002 · D.M. Wu, J. Waicukauski · IEEE International Symposium on Circuits and Systems proceedings · 5
Defect analysis and test generation for gate oxide shorts in CMOS ICs
2002 · S.I. Syed, D.M. Wu · Custom Integrated Circuits Conference · 4
Improve yield and quality through testability analysis of VLSI circuits
1984 · D.M. Wu, C. C. Beh, et al. · IEEE International Test Conference (ITC) · 4
Direct 3D lossless image compression based on regiongrowing
2000 · D. Wu, E.C. Tan · Electronics Letters · 3
Low-Area-Cost VLSI Architecture of Fault-Aware High-Reliability Triple-Mode Polar Decoder Chip Reconfiguring SC and SCL Decoding
2025 · Xin-Yu Shih, Dong-Lin Wu, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2
Energy-Efficient Connectivity Algorithm for Directional Sensor Networks in Edge Intelligence Systems
2024 · Dingcheng Wu, Xueyong Xu, et al. · Symmetry · 2
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Built-in self test using perturbed deterministic patterns
2003 · D.M. Wu, J. Waicukauski · 2
Multiple redundancy removal during test generation and synthesis
2003 · D.M. Wu, R.M. Swanson · IEEE VLSI Test Symposium (VTS) · 2
Enhancing GNSS Positioning Using Transformer-Based Correction Network
2024 · Changyi Zhu, Xueyong Xu, et al. · Proceedings of the Satellite Division's International Technical Meeting (Online)/Proceedings of the Satellite Division's International Technical Meeting (CD-ROM) · 1
CMOS stuck-open fault modeling, detection and simulation
2003 · D.M. Wu, E.P. Hsieh · IEEE International Symposium on Circuits and Systems proceedings · 1
Automatic fault model/logic model generation for large scale ASIC circuits
2002 · D.M. Wu, M. Dibrino · Annual IEEE International ASIC Conference and Exhibit · 1
Design and test strategy for differential cascode voltage switch circuits
2002 · D.M. Wu, J.W. Davis, et al. · Annual IEEE International ASIC Conference and Exhibit · 1
A Reliability Evaluation Method for Energy Routers Based on Directed Graphs and Minimum Cost Maximum Flow
2025 · Zhigang Song, Ling Hong, et al. · International Conference on Power and Renewable Energy (ICPRE)
Research on Distributed Double Redundancy Flap
2025 · Diancheng Wu, Gaojie Ma, et al. · Lecture notes in electrical engineering
Works count: 32
Citation count: 373
H-index: 10
I10-index: 10
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