Get started
Author

Taehyoun Oh

Observed names: T. Oh, Tae-Hyoun Oh, TaeHyoun Oh
ORCID: 0000-0002-6574-0590
Observed ORCID: 0000-0002-6574-0590
OpenAlex ID: A5101812214
A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os
2011 · Taehyoun Oh, Ramesh Harjani · IEEE Journal of Solid-State Circuits · 41
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS
2013 · Taehyoun Oh, R. Harjani · IEEE Journal of Solid-State Circuits · 40
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process
2024 · Kyoung-Ub Cho, Joonho Gil, et al. · IEEE Access · 12
A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os
2010 · Taehyoun Oh, Ramesh Harjani · Custom Integrated Circuits Conference · 12
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS
2012 · Taehyoun Oh, Ramesh Harjani · Symposium on VLSI Circuits · 9
Adaptive Techniques for Joint Optimization of XTC and DFE Loop Gain in High-Speed I/O
2015 · Taehyoun Oh, Ramesh Harjani · ETRI Journal · 7
PDF
A 8.9 to 10-GHz −97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process
2025 · Sangwon Kim, Kihoon Kwon, et al. · IEEE Access · 4
Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL
2021 · Taehyoun Oh, Joonho Gil, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 4
Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS
2022 · Sanggeun Lee, Ramesh Harjani, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 3
A Highly Integrated Radio Frequency Receiver RF CMOS Module for Core Body Temperature Thermometer
2023 · Ikhwan Kim, Wonil Jang, et al. · IEEE Access · 2
PDF
12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme
2019 · K. Park, T. Oh · Electronics Letters · 2
PDF
A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process
2026 · Kihoon Kwon, Sangwon Kim, et al. · IEEE Access · 1
A 5.3 to 6.2-GHz Fractional-N Frequency Synthesizer with Variable Gain Automatic Frequency Calibration Using Cycle Slips in 65 nm CMOS
2025 · Jinhyuk Ahn, Sangwon Kim, et al. · Electronics · 1
0.5–4.4 Gbit/s PAM4/NRZ dual‐mode transceiver with 0.6 V near‐ground NMOS driver for low‐power memory interface
2018 · K. Min, T. Oh · Electronics Letters · 1
PDF
Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process
2017 · E. Kim, T. Oh · Electronics Letters · 1
A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process
2016 · Esther Kim, Deokgwan Jeong, et al. · International SoC Design Conference · 1
Adaptive XTCR, AGC, and Adaptive DFE Loop
2013 · Taehyoun Oh, Ramesh Harjani · Analog circuits and signal processing/Analog circuits and signal processing series · 1
Research Summary and Contributions
2013 · Taehyoun Oh, Ramesh Harjani · Analog circuits and signal processing/Analog circuits and signal processing series · 1
High Performance Multi-Channel High-Speed I/O Circuits
2013 · Taehyoun Oh, Ramesh Harjani · Analog circuits and signal processing/Analog circuits and signal processing series · 1
Fully Integrated X-Band CMOS RF Transceiver for Data Communications
2026 · Won-il Jang, Yong-Ho Kim, et al. · The Journal of Korean Institute of Electromagnetic Engineering and Science
PDF
A Highly Integrated CMOS Dicke Radiometer IC for Remote Thermometer Applications
2025 · Jin Mo Kim, Hyeon Sik Hwang, et al. · Asia-Pacific Microwave Conference (APMC)
Low-Power Narrowband 433 MHz Transceiver IC for Long-Range Drone Communication
2025 · Gisung Lee, Dongwuk Park, et al. · The Journal of Korean Institute of Electromagnetic Engineering and Science
PDF
2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process
2024 · Goohyung Chung, Kyoungub Cho, et al. · JSTS Journal of Semiconductor Technology and Science
High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process
2021 · Kyunghwan Min, Sanggeun Lee, et al. · JSTS Journal of Semiconductor Technology and Science
12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process
2021 · Sanggeun Lee, Taehyoun Oh · JSTS Journal of Semiconductor Technology and Science
Works count: 34
Citation count: 144
H-index: 6
I10-index: 4
Year
Topic
Type