Get started
Author

Yuchun Ma

Observed names: Ma Yuchun, Ma, Yuchun, Y. Ma, YUCHUN MA, Yu-Chun Ma, Yuchun MA
Observed institutions: Pennsylvania State University, University of California, Los Angeles, Hunan University, Hainan Tropical Ocean University, Northeastern University, Tsinghua University
ORCID: 0000-0003-3160-6681
Observed ORCID: 0000-0003-3160-6681
OpenAlex ID: A5102025379
F-CNN: An FPGA-based framework for training Convolutional Neural Networks
2016 · Wenlai Zhao, Haohuan Fu, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 123
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
2007 · Pingqiang Zhou, Yuchun Ma, et al. · 77
An automated design flow for 3D microarchitecture evaluation
2006 · J. Cong, A. Jagannathan, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 50
General Application Research on GSM Module
2011 · Ma Yuchun, Huang Yinghong, et al. · International Conference on Internet Computing and Information Services · 40
VLSI floorplanning with boundary constraints based on corner block list
2001 · Yuchun Ma, Sheqin Dong, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 40
AddressNet: Shift-Based Primitives for Efficient Convolutional Neural Networks
2019 · Yihui He, Xianggen Liu, et al. · IEEE Winter Conference on Applications of Computer Vision · 33
Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list
2001 · Yuchun Ma, Xianlong Hong, et al. · ACM/IEEE Design Automation Conference (DAC) · 31
Simultaneous buffer and interlayer via planning for 3D floorplanning
2009 · Xu He, Sheqin Dong, et al. · International Symposium on Quality Electronic Design (ISQED) · 30
A novel thermal optimization flow using incremental floorplanning for 3D ICs
2009 · Xin Li, Yuchun Ma, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 30
Fine grain 3D integration for microarchitecture design through cube packing exploration
2007 · Yongxiang Liu, Yuchun Ma, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 28
PDF
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
2007 · Jiayi Liu, Sheqin Dong, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 26
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization
2011 · Xiaoming Chen, Yu Wang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 24
Shift-based Primitives for Efficient Convolutional Neural Networks
2018 · Zhong, Huasong, Liu, Xianggen, et al. · arXiv (Cornell University) · 19
PDF
Buffer planning as an Integral part of floorplanning with consideration of routing congestion
2005 · Yuchun Ma, Xianlong Hong, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 19
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
2003 · Yuchun Ma, Xianlong Hong, et al. · ACM/IEEE Design Automation Conference (DAC) · 19
Thermal-aware power network design for IR drop reduction in 3D ICs
2012 · Zuowei Li, Yuchun Ma, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 18
Circuit-level delay modeling considering both TDDB and NBTI
2011 · Hong Luo, Xiaoming Chen, et al. · International Symposium on Quality Electronic Design (ISQED) · 18
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
2009 · Xiaoming Chen, Yu Wang, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 17
Design space exploration for 3D integrated circuits
2008 · Yuan Xie, Yuchun Ma · IEEE International Conference on Solid-State and Integrated Circuit Technology · 17
Modular Placement for Interposer based Multi-FPGA Systems
2016 · Fubing Mao, Wei Zhang, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 16
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
2007 · Yuchun Ma, Zhuoyuan Li, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 16
Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs
2013 · Ning Xu, Yu-Chun Ma, et al. · Journal of Computer Science and Technology · 15
TSV-aware topology generation for 3D Clock Tree Synthesis
2013 · Wulong Liu, Haixiao Du, et al. · International Symposium on Quality Electronic Design (ISQED) · 15
3D CBL: An Efficient Algorithm for General 3-Dimensional Packing Problems *
2005 · Yuchun Ma, Xianlong Hong, et al. · 15
HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs
2014 · Yuchun Ma, Jinglan Liu, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 13
Works count: 123
Citation count: 1,072
H-index: 17
I10-index: 34
Year
Topic
Type