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Hsing-Hui Hsu

OpenAlex ID: A5102158510
Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors
2009 · Horng-Chih Lin, Cheng-Hsiung Hung, et al. · Journal of Applied Physics · 38
Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations
2008 · Hsing-Hui Hsu, Ta-Wei Liu, et al. · IEEE Transactions on Electron Devices · 34
A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate
2008 · Horng-Chih Lin, Hsing-Hui Hsu, et al. · IEEE Electron Device Letters · 20
Threshold-Voltage Fluctuation of Double-Gated Poly-Si Nanowire Field-Effect Transistor
2009 · Hsing-Hui Hsu, Horng-Chih Lin, et al. · IEEE Electron Device Letters · 13
Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS Devices
2011 · Hsing-Hui Hsu, Horng-Chih Lin, et al. · IEEE Transactions on Electron Devices · 10
Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices
2011 · Cheng-Wei Luo, Horng-Chih Lin, et al. · IEEE Transactions on Electron Devices · 8
Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices
2010 · Hsing-Hui Hsu, Horng-Chih Lin, et al. · IEEE Transactions on Electron Devices · 7
Trigated Poly-Si Nanowire SONOS Devices for Flat-Panel Applications
2009 · Horng-Chih Lin, Ta-Wei Liu, et al. · IEEE Transactions on Nanotechnology · 5
Characteristics of Poly-Si Nanowire Transistors with Multiple-Gate Configurations
2008 · Hsing-Hui Hsu, Horng-Chih Lin, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 4
Tri-gated poly-Si nanowire SONOS devices
2009 · Hsing-Hui Hsu, Ta-Wei Liu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
Impacts of gap thickness scaling on Thin-Film Transistors with suspended nanowire channels
2011 · Chia-Hao Kuo, Chia-Wei Hsu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 2
Investigations of performance enhancement in a poly-Si nanowire FET featuring independent double-gated configuration and its nonvolatile memory applications
2010 · Wei-Chen Chen, Hsing-Hui Hsu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 1
Impacts of multiple-gate configuration on characteristics of poly-Si nanowire SONOS devices
2010 · Hsing-Hui Hsu, Shuan-Yun Huang, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 1
Fabrication and characterization of a novel suspended-nanowire-channel thin-film transistor with nanometer air gap
2011 · Chia-Wei Hsu, Chia-Hao Kuo, et al. · IEEE International Conference on Nano/Micro Engineered and Molecular Systems
Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layer
2009 · Ko-Hui Lee, Hsing-Hui Hsu, et al. · Japanese Journal of Applied Physics
Tri-gate poly-Si thin-film transistor with nanowire channels
2008 · Hsing-Hui Hsu, Homg-Chih Lin, et al. · IEEE Silicon Nanoelectronics Workshop
Works count: 16
Citation count: 146
H-index: 7
I10-index: 5
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