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Byung‐Hun Min

Observed names: Byung-Hun Min, Byunghun Min
OpenAlex ID: A5102252212
A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation
2012 · Ja-Yol Lee, Mi-Jeong Park, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 32
5-GHz CMOS LC VCOs with wide tuning ranges
2005 · Byunghun Min, Hanggeun Jeong · IEEE Microwave and Wireless Components Letters · 24
1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector
2013 · Sangjin Byun, Chung Hwan Son, et al. · IET Circuits Devices & Systems · 10
Low Voltage CMOS LC VCO with Switched Self-Biasing
2009 · Byung-Hun Min, Seok-Bong Hyun, et al. · ETRI Journal · 9
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A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip
2011 · Hoai-Nam Nguyen, Seung-Hwan Jung, et al. · European Solid-State Circuits Conference (ESSCIRC) · 3
A low-power small-size transmitter with discrete-time baseband filter for LTE in 65 nm CMOS
2013 · Hoai-Nam Nguyen, Jang-Hong Choi, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 1
Carrier Cancelling RF for Multi-Mode SDR Terminal Applicable to CDMA-Cellular, WCDMA, and WiBro
2007 · Byoung Gun Choi, Byunghun Min, et al. · International Symposium on Signals, Systems and Electronics · 1
A New CMOS LC VCO Structure for Wide Tuning Range
2004 · Byung‐Hun Min, Hang-Geun Jeong · 대한전자공학회 ISOCC
A Ring Oscillator with a New Load Cell for Improved Linearity
2004 · Byung‐Hun Min, Hang-Geun Jeong · 대한전자공학회 ISOCC
Works count: 9
Citation count: 80
H-index: 4
I10-index: 3
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