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Author

Wenji Fang

Observed names: Fang, Wenji, Wenji, FANG
ORCID: 0000-0002-8380-9395
Observed ORCID: 0000-0002-8380-9395
OpenAlex ID: A5102873255
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
2024 · Shang Liu, Wenji Fang, et al. · IEEE LLM Aided Design Workshop (LAD) · 166
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RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
2024 · Shang Liu, Wenji Fang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 101
Large circuit models: opportunities and challenges
2024 · Lei Chen, Yiqi Chen, et al. · Science China Information Sciences · 86
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AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
2024 · Wenji Fang, Mengming Li, et al. · IEEE LLM Aided Design Workshop (LAD) · 61
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
2023 · Wenji Fang, Yao Lu, et al. · 59
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AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
2024 · Fang, Wenji, Li, Mengming, et al. · arXiv (Cornell University) · 56
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OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
2024 · Shang Liu, Yao Lu, et al. · 52
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AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
2025 · Zhiyuan Yan, Wenji Fang, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 46
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A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
2026 · Wenji Fang, Jing Wang, et al. · ACM Transactions on Design Automation of Electronic Systems · 39
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
2025 · Mengming Li, Wenji Fang, et al. · International Symposium of Electronics Design Automation (ISEDA) · 35
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NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
2025 · Wenji Fang, Wenkai Li, et al. · ACM/IEEE Design Automation Conference (DAC) · 20
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Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
2024 · Wenji Fang, Yao Lu, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 15
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
2024 · Wenji Fang, Shang Liu, et al. · ACM/IEEE Design Automation Conference (DAC) · 13
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Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
2026 · Fang, Wenji, Lu, Yao, et al. · arXiv (Cornell University) · 10
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A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
2025 · Wenji Fang, Shang Liu, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 10
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CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
2025 · Fang, Wenji, Liu, Shang, et al. · arXiv (Cornell University) · 8
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A New Benchmark for the Appropriate Evaluation of RTL Code Optimization
2026 · Lu, Yao, Liu, Shang, et al. · arXiv (Cornell University) · 7
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r-map: Relating Implementation and Specification in Hardware Refinement Checking
2023 · Wenji Fang, Guangyu Hu, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 6
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
2025 · Shang Liu, Wenji Fang, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 5
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
2026 · Wang, Jing, Liu, Shang, et al. · arXiv (Cornell University) · 4
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ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
2025 · Wenkai Li, Yao Lu, et al. · ACM/IEEE Design Automation Conference (DAC) · 4
Profile-Guided Temporal Prefetching
2025 · Mengming Li, Qijun Zhang, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 4
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SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
2025 · Shang Liu, Jing Wang, et al. · ACM/IEEE Design Automation Conference (DAC) · 3
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A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis
2026 · Wenkai Li, Yao Lu, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2
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GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
2025 · Wenji Fang, Wang Jing, et al. · 2
Works count: 41
Citation count: 822
H-index: 13
I10-index: 15
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