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Yu-Hao Hsu

ORCID: 0000-0002-3165-1960
Observed ORCID: 0000-0002-3165-1960
OpenAlex ID: A5102914090
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
2023 · Haruki Mori, Wei-Chang Zhao, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 119
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector
2014 · Fan-Ta Chen, Min-Sheng Kao, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 30
20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network
2013 · Min-Sheng Kao, Fan-Ta Chen, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 17
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking
2023 · Yumito Aoyagi, Makoto Yabuuchi, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 13
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit
2011 · Fan-Ta Chen, Min-Sheng Kao, et al. · IEEE International Symposium on Circuits and Systems proceedings · 8
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture
2024 · Masaru Haraguchi, Yorinobu Fujino, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 5
A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
2024 · Yumito Aoyagi, Koji Nii, et al. · IEEE Journal of Solid-State Circuits · 5
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications
2007 · Ching-Te Chiu, Yu-Hao Hsu, et al. · IEEE International Symposium on Circuits and Systems proceedings · 5
Low Propagation Delay Load-Balanced 4$\,\times\,$4 Switch Fabric IC in 0.13-$\mu{\rm m}$ CMOS Technology
2012 · Ching-Te Chiu, Yu-Hao Hsu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 4
A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
2024 · Masaru Haraguchi, Yorinobu Fujino, et al. · IEEE Journal of Solid-State Circuits · 3
A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications
2024 · Ming-Chieh Huang, Wei Wing Mar, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 3
A 3-nm FinFET 563-kbit 35.5-Mbit/mm 2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode
2025 · Yumito Aoyagi, Koji Nii, et al. · IEEE Journal of Solid-State Circuits · 2
A 3nm FinFET 563kbit 35.5Mbit/mm2 Dual-Rail SRAM with 3.89pJ/Access High Energy Efficient andμW/Mbit 1-Cycle Latency Low-Leakage Mode
2025 · Yumito Aoyagi, Makoto Yabuuchi, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2
A Quarter-Rate 2.56/3.2 Gbps 16/20:1 SERDES Interface in 0.18um CMOS Technology
2009 · Yu-Hao Hsu, Ming-Hao Lu, et al. · 2
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13μm CMOS technology
2008 · Yu-Hao Hsu, Ming-Hao Lu, et al. · IEEE International Symposium on Circuits and Systems proceedings · 2
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces
2007 · Yu-Hao Hsu, Min-Sheng Kao, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 1
A 2nm 234.4 TOPS/W and 511.9 $\text{TOPS}/\text{mm}^{2}$ Digital Computing-in-Memory Compiler with Multiple MAC Units per Weight and Multiple Data Format Support
2026 · Hidehiro Fujiwara, Brian Crafton, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology
2011 · Yu-Hao Hsu, Yang-Syu Lin, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC)
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking
2010 · Ching-Te Chiu, Yu-Hao Hsu, et al. · Journal of Signal Processing Systems
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology
2010 · Yu-Hao Hsu, Yang-Syu Lin, et al. · IEEE International Symposium on Circuits and Systems proceedings
Works count: 20
Citation count: 221
H-index: 5
I10-index: 4
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