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Yan Wang

A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links
2014 · Yong Chen, Pui-In Mak, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 30
A 0.002-mm $^{2}$ 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency
2014 · Yong Chen, Pui-In Mak, et al. · IEEE Transactions on Microwave Theory and Techniques · 28
An all digital phase-locked loop based on double edge triggered flip-flop
2006 · Chang-hong Shan, Zhong-ze Chen, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 10
Adjoint Transient Sensitivity Analysis for Objective Functions Associated to Many Time Points
2020 · Wenfei Hu, Zuochang Ye, et al. · ACM/IEEE Design Automation Conference (DAC) · 8
A 60GHz 360° digitally controlled phase shifter with 6-bit resolution and 2.3° maximal rms phase error in 65nm CMOS technology
2015 · Dong Huang, Lei Zhang, et al. · IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) · 6
A 56-to-66 GHz quadrature phase-locked loop with a wide locking range divider chain in 65nm CMOS
2015 · Bin Zhou, Lei Zhang, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · 6
A 50% duty cycle wide-locking range divide-by-3 divider up to 6GHz
2011 · Chunyuan Zhou, Lei Zhang, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 4
A Low Power High Swing Charge Pump for Phase Locked Loops
2023 · Wei Zhang, Ke Chang, et al. · 3
A Half-rate Bang-bang Clock and Data Recovery Circuit for 56 Gb/s PAM4 Receiver in 65 nm CMOS
2021 · Xingjian Yangdong, Qingsheng Hu, et al. · International Conference on Integrated Circuits and Microsystems (ICICM) · 2
A high-speed PAM4 transmitter with T-coil peaking in 65 nm CMOS technology
2025 · Yan Wang, Qingsheng Hu, et al. · Microelectronics Journal · 1
A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper
2021 · Zexin Yuan, Lei Zhang, et al. · IEEE International Symposium on Circuits and Systems proceedings · 1
A 140GHz phase-locked loop with 14.3% locking range in 65-nm CMOS
2017 · Lei Zhang, Lin Lin, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · 1
Clock Noise and Disordered Measurements
2015 · Yan Wang · Springer theses · 1
A 1.8v low-jitter clock generator for 1000 Base-T Ethernet Transceiver
2005 · Ping Lu, Yan Wang, et al. · Fudan xuebao. Ziran Kexue ban · 1
A new time-frequency synchronisation algorithm based on preamble sequence in OFDM system
2025 · Yanli Hou, Yan Wang, et al. · International Journal of Wireless and Mobile Computing
Full-Chip Harmonic Balance Analysis in Parallel
2022 · Sen-Hua Dong, Xiao-Lue Lai, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology
A 68.1-to-73.8GHz E-band low phase noise QPLL with amplifier feedback QVCO in 65-nm CMOS
2017 · Xinxin Zhu, Lei Zhang, et al. · IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Quantizer Design for Codebook-Based Beamforming in Temporally-Correlated Channels
2008 · Pengcheng Zhu, Lan Tang, et al. · Globecom
Works count: 18
Citation count: 102
H-index: 6
I10-index: 3
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