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Hans Jacobson

Observed names: H. JACOBSON, H. Jacobson, Hans M. Jacobson
ORCID: 0009-0000-1858-8883
Observed ORCID: 0009-0000-1858-8883
OpenAlex ID: A5108277262
Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors
2000 · P.W. Cook, M. Gupta, et al. · IEEE Micro · 507
Microarchitectural techniques for power gating of execution units
2004 · Zhigang Hu, Alper Buyuktosunoglu, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 393
Quantifying sources of error in McPAT and potential impacts on architectural studies
2015 · Sam Likun Xi, Hans Jacobson, et al. · Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings · 103
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
2005 · H. Jacobson, P. Bose, et al. · Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings · 45
Abstraction and microarchitecture scaling in early-stage power modeling
2011 · Hans Jacobson, Alper Buyuktosunoglu, et al. · Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings · 38
Power management of multi-core chips: Challenges and pitfalls
2012 · P. Bose, A. Buyuktosunoglu, et al. · Design, Automation, and Test in Europe · 30
A technique for synthesizing distributed burst-mode circuits
1996 · Prabhakar Kudva, Ganesh Gopalakrishnan, et al. · Proceedings - ACM IEEE Design Automation Conference · 29
High-level asynchronous system design using the ACK framework
2002 · H. Jacobson, E. Brunvand, et al. · Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems · 24
Power optimization methodology for the IBM POWER7 microprocessor
2011 · V. Zyuban, J. Friedrich, et al. · IBM Journal of Research and Development · 19
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor
2003 · P. Bose, D. Brooks, et al. · Lecture notes in computer science · 19
Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes
1996 · Prabhakar Kudva, Ganesh Gopalakrishnan, et al. · Proceedings - ACM IEEE Design Automation Conference · 18
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Energy Efficiency Boost in the AI-Infused POWER10 Processor
2021 · Brian W. Thompto, Dung Q. Nguyen, et al. · ACM/IEEE International Symposium on Computer Architecture (ISCA) · 14
Thermal analysis of multi-layer functional 3D logic stacks
2016 · M. Scheuermann, S. Tian, et al. · IEEE International D Systems Integration Conference · 9
Very Low Voltage (VLV) Design
2017 · Ramon Bertran, Pradip Bose, et al. · Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design · 7
Power management of multi-core chips: challenges and pitfalls
2012 · Pradip Bose, Alper Buyuktosunoglu, et al. · Design, Automation, and Test in Europe · 7
Generation of Stressmarks for Early Stage Soft-Error Modeling
2019 · Karthik Swaminathan, Ramon Bertran, et al. · IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S) · 6
Empirically derived abstractions in uncore power modeling for a server-class processor chip
2014 · Hans Jacobson, Arun Joseph, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 6
Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines
2000 · Hans Jacobson, Chris J. Myers, et al. · 5
Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines
2002 · H. Jacobson, C. Myers, et al. · International Conference on Computer Aided Design · 4
SERMiner : A Framework for Early-stage Reliability Estimation for IBM Processors
2021 · Karthik Swaminathan, Ramon Bertran, et al. · IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S) · 3
Power-efficient, reliable microprocessor architectures
2010 · Pradip Bose, Alper Buyuktosunoglu, et al. · 3
Efficient exact two-level hazard-free logic minimization
2002 · C. Myers, H. Jacobson · 3
Robust Power Management: A Key Aspect of Silent Data Corruption-Free Systems
2025 · Pradip Bose, Ramon Bertran, et al. · IEEE Micro
Characterization and Exploration of Latch Checkers for Efficient RAS Protection
2023 · Karthik Swaminathan, Ramon Bertran, et al. · IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)
Session details: Photonics, spintronics, approximate computing and front-end throttling
2014 · Hans Jacobson, Umit Ogras · International Symposium on Low Power Electronics and Design (ISLPED)
Works count: 27
Citation count: 1,292
H-index: 12
I10-index: 12
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