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Seshasayanan Ramachandran

Observed names: Ramachandran. S, S Ramachandran, S. RAMACHANDRAN, S. Ramachandran, S.S. Ramachandran, Seshasayanan RAMACHANDRAN, Sundaresan Ramachandran
Observed institutions: Jawaharlal Nehru Technological University, Hyderabad, Anna University, Chennai, Naif Arab University for Security Sciences, Goodyear (United States), Gnanamani College of Technology, Goodyear Aerospace (United States), Ramaiah Institute of Technology, Indian Institute of Science Bangalore, Sri Sivasubramaniya Nadar College of Engineering
ORCID: 0009-0003-9650-8078
Observed ORCID: 0009-0003-9650-8078
OpenAlex ID: A5108661602
Robust Digital image Watermarking Algorithm in DWT-DFT-SVD domain for color images
2012 · Rahim Ansari, Mrutyunjaya M Devanalamath, et al. · International Conference on Communication, Information & Computing Technology · 32
Area and power efficient DCT architecture for image compression
2014 · Vaithiyanathan Dhandapani, Seshasayanan Ramachandran · EURASIP Journal on Advances in Signal Processing · 30
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Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture
2012 · S. Ramachandran, Kirti S. Pande · 22
Design and FPGA implementation of modified Distributive Arithmetic based DWT-IDWT processor for image compression
2011 · M. Nagabushanam, P Cyril Prasanna Raj, et al. · International Conference on Communications and Signal Processing (ICCSP) · 16
Design of a 1-bit half and full subtractor using a quantum-dot cellular automata (QCA)
2017 · S.S. Ramachandran, K. J. Jegadish Kumar · IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI) · 13
Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression
2012 · M. Nagabushanam, S. Ramachandran · International Journal of Computer Applications · 10
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NULL Convention Floating Point Multiplier
2015 · Anitha Juliette Albert, Seshasayanan Ramachandran · The Scientific World JOURNAL · 6
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Enhancing Ransomware Threat Detection: Risk-Aware Classification via Windows API Call Analysis and Hybrid ML/DL Models
2025 · Sarah Alhuwayshil, Sundaresan Ramachandran, et al. · Journal of Cybersecurity and Privacy · 5
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FPGA Implementation of 1D and 2D DWT Architecture using Modified Lifting Scheme
2013 · M. Nagabushanam, S. Ramachandran, et al. · 5
An optimised twin precision multiplier for ASIC environment
2015 · Rosi Asirvatham, Seshasayanan Ramachandran · EURASIP Journal on Advances in Signal Processing · 4
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Power-optimized log-based image processing system
2014 · Vaithiyanathan Dhandapani, Seshasayanan Ramachandran · EURASIP Journal on Image and Video Processing · 4
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Data security using serial commutative RSA CORE for multiple FPGA system
2014 · R. Ambika, S. Ramachandran, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 4
Fast Implementation of Lifting Based DWT Architecture For Image Compression
2012 · M. Nagabushanam, S. Ramachandran · Global Journal of Computer Science and Technology · 4
Performance analysis on color image mosaicing techniques on FPGA
2019 · Jayalaxmi H, S. Ramachandran · International Journal of Electrical and Computer Engineering (IJECE) · 2
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An Efficient Hardware Realization of DCT Based Color Image Mosaicing System on FPGA
2018 · H. Jayalaxmi, S. Ramachandran · Advances in intelligent systems and computing · 2
Design of Commutative Cryptography Core with Key Generation for Distributed FPGA Architecture
2014 · R. Ambika, S. Ramachandran · 2
FPGA Implementation of an Efficient VLSI Architecture for Lift Based 5/3 DWT
2014 · Professor, E&C, SDMIT, Ujire ,India, Shriram P Hegde, et al. · IOSR Journal of VLSI and Signal processing · 2
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Securing Distributed FPGA System using Commutative RSA Core
2013 · R. Ambika, S. Ramachandran, et al. · Global Journal of Researches in Engineering · 2
Modified VLSI implementation of DA-DWT for image compression
2012 · M. Nagabushanam, P. Cyril Prasanna Raj, et al. · International Journal of Signal and Imaging Systems Engineering · 2
Improved g-cueing system
1982 · E.B. Bose, W.P. Leavy, et al. · Journal of Aircraft · 2
Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure
2020 · Nirmaladevi Ramu, Seshasayanan Ramachandran · Circuit World · 1
An optimized embedded adder for digital signal processing applications
2016 · Kala BHARATHAN, Seshasayanan RAMACHANDRAN · TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES · 1
TA-4J Spin Training Through Simulation
1982 · S. Ramachandran, R.T. Galloway · Journal of Aircraft · 1
A New Public Key Cipher System based on Linear Transforms with Elliptic Curve Arithmetic for Secured Communication
2024 · S Ramachandran, Sindhu J Kumaar · Research Square
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Fault Testing and Diagnosis of Sram based FBGA using Built-In-Self-Test-Architecture
2018 · Nagma. P, Ramachandran. S, et al. · International Journal of Trend in Scientific Research and Development
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Works count: 33
Citation count: 172
H-index: 6
I10-index: 6
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