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R. Takemura

Observed names: R Takemura, R. TAKEMURA, Riichiro TAKEMURA, Riichiro Takemura, Riichiro Takemura Riichiro Takemura
Institution: Hitachi (Japan)
OpenAlex ID: A5109081609
Spin-transfer torque RAM technology: Review and prospect
2011 · T. Kawahara, K. Ito, et al. · Microelectronics Reliability · 326
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read
2008 · Takayuki Kawahara, Riichiro Takemura, et al. · IEEE Journal of Solid-State Circuits · 225
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read
2007 · T. Kawahara, R. Takemura, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 218
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme
2010 · Riichiro Takemura, Takayuki Kawahara, et al. · IEEE Journal of Solid-State Circuits · 129
A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions
2010 · T. Ishigaki, T. Kawahara, et al. · Symposium on VLSI Technology · 107
Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers
2008 · J. Hayakawa, S. Ikeda, et al. · IEEE Transactions on Magnetics · 93
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Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond
2010 · R. Takemura, T. Kawahara, et al. · IEEE International Memory Workshop (IMW) · 51
A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM
2009 · K. Ono, T. Kawahara, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 43
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router
2005 · S. Hanzawa, T. Sakata, et al. · IEEE Journal of Solid-State Circuits · 41
Oxygen-doped gesbte phase-change memory cells featuring 1.5 V/100-μA standard 0.13μm CMOS operations
2006 · N. Matsuzaki, K. Kurotsuchi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 33
A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations
2004 · N. Takaura, M. Terao, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 33
A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse
2001 · T. Takahashi, T. Sekiguchi, et al. · IEEE Journal of Solid-State Circuits · 32
A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion
2007 · K. Miura, T. Kawahara, et al. · Symposium on VLSI Technology · 21
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays
2009 · S. Akiyama, T. Sekiguchi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 18
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs
2007 · Kiyoo Itoh, Riichiro Takemura · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 17
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory
2006 · K. Osada, T. Kawahara, et al. · Custom Integrated Circuits Conference · 14
Atomically flat OMVPE growth of GaInAs and InP observed by AFM for level narrowing in resonant tunneling diodes
1997 · Michihiko Suhara, Chuma Nagao, et al. · Journal of Crystal Growth · 13
Effect of Spacer Layer Thickness on Energy Level Width Narrowing in GaInAs/InP Resonant Tunneling Diodes Grown by Organo-Metallic Vapor Phase Epitaxy
1998 · Takashi Oobo Takashi Oobo, Riichiro Takemura Riichiro Takemura, et al. · Japanese Journal of Applied Physics · 11
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TMR Design Methodology for SPin-Transfer Torque RAM (SPRAM) with Nonvolatile and SRAM Compatible Operations
2008 · R. Takemura, T. Kawahara, et al. · IEEE International Memory Workshop (IMW) · 10
SPRAM with large thermal stability for high immunity to read disturbance and long retention for high-temperature operation
2006 · Kyosuke Ono, T. Kawahara, et al. · Symposium on VLSI Technology · 10
Characterization of GaInAs/InP Triple-Barrier Resonant Tunneling Diodes Grown by Organo-Metallic Vapor Phase Epitaxy for High-Temperature Estimation of Phase Coherent Length of Electrons
1997 · Riichiro Takemura Riichiro Takemura, Michihiko Suhara Michihiko Suhara, et al. · Japanese Journal of Applied Physics · 10
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A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers
2006 · Riichiro Takemura, Kiyoo Itoh, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 9
A dynamic CAM - based on a one-hot-spot block code - for millions-entry lookup
2004 · S. Hanzawa, T. Sakata, et al. · Symposium on VLSI Circuits · 9
High Peak-to-Valley Current Ratio GaInAs/GaInP Resonant Tunneling Diodes
1997 · Takashi Oobo Takashi Oobo, Riichiro Takemura Riichiro Takemura, et al. · Japanese Journal of Applied Physics · 9
In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise 4F 2 DRAM array operable at 10-fF cell capacitance
2011 · Yoshimitsu Yanagawa, T. Sekiguchi, et al. · Symposium on VLSI Circuits · 8
Works count: 72
Citation count: 1,586
H-index: 15
I10-index: 21
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