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Jürgen Maier

Observed names: Jurgen Maier, Jürgen Burin, Maier, Jürgen, Maier, Jürgen; orcid:0000-0002-0965-5746
Observed institutions: Centre National de la Recherche Scientifique, Austrian Academy of Sciences, TU Wien, École Normale Supérieure - PSL, Institute of High Energy Physics, MBI - Marietta-Blau-Institut für Teilchenphysik
ORCID: 0000-0002-0965-5746
Observed ORCID: 0000-0002-0965-5746
OpenAlex ID: A5109158696
The Involution Tool for Accurate Digital Timing and Power Analysis
2020 · Daniel Öhlinger, Jürgen Maier, et al. · Integration · 17
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Verifying nonlinear analog and mixed-signal circuits with inputs
2018 · Chuchu Fan, Yu Meng, et al. · IFAC-PapersOnLine · 16
A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate
2022 · Arman Ferdowsi, Jurgen Maier, et al. · Design, Automation, and Test in Europe · 11
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The Metastable Behavior of a Schmitt-Trigger
2016 · Andreas Steininger, Jurgen Maier, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 10
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The Hidden Behavior of a D-Latch
2023 · Jürgen Maier, Andreas Steininger, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 8
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Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses
2021 · Jurgen Maier, Christian Hartl-Nesic, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 8
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A faithful binary circuit model with adversarial noise
2018 · Matthias Fugger, Jurgen Maier, et al. · Design, Automation, and Test in Europe · 7
A Composable Glitch-Aware Delay Model
2021 · Jürgen Maier, Daniel Öhlinger, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 6
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Detector development for particle physics
2024 · Simon Waid, Jürgen Maier, et al. · e+i Elektrotechnik und Informationstechnik · 4
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Detector Development for Particle Physics
2023 · Simon Waid, Jürgen Maier, et al. · Austrochip Workshop on Microelectronics (Austrochip) · 4
The Involution Tool for Accurate Digital Timingand Power Analysis
2019 · Daniel Ohlinger, Jurgen Maier, et al. · International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) · 4
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Transistor-Level Analysis of Dynamic Delay Models
2019 · Jurgen Maier, Matthias Fugger, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 4
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Atomistic modeling of interfaces in III–V semiconductor superlattices
2016 · Jürgen Maier, Hermann Detz · physica status solidi (b) · 4
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Gain and Pain of a Reliable Delay Model
2021 · Jurgen Maier · Euromicro Conference on Digital System Design (DSD) · 2
Gain and Pain of a Reliable Delay Model
2021 · Jürgen Maier · 2
A Faithful Binary Circuit Model with Adversarial Noise
2020 · Függer, Matthias, Maier, Jürgen, et al. · arXiv (Cornell University) · 2
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Efficient Metastability Characterization for Schmitt-Triggers
2019 · Jurgen Maier, Andreas Steininger · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 2
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Online Test Vector Insertion -- A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic
2014 · Maier, Jürgen · reposiTUm (TU Wien) · 2
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Gain and Pain of a Reliable Delay Model
2021 · Jürgen Maier · 1
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512-channel SiC beam monitor electronics: single-particle up to clinical beam rates using commercial components
2026 · Richard Thalmeier, Simon Emanuel Waid, et al. · Journal of Instrumentation
Gain and Pain of a Reliable Delay Model
2021 · Jürgen Maier
Gain and Pain of a Reliable Delay Model
2021 · Maier, Jürgen · arXiv (Cornell University)
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Unified (A)Synchronous Circuit Development
2019 · Philipp Paulweber, Jürgen Maier, et al. · reposiTUm (TU Wien)
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Works count: 26
Citation count: 115
H-index: 7
I10-index: 4
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