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R. K. Siddharth

Observed names: R.K. Siddharth, Siddharth R. K, Siddharth R. K., Siddharth R.K., Siddharth Rajkumar Kala
ORCID: 0000-0003-2280-9903
Observed ORCID: 0000-0003-2280-9903
OpenAlex ID: A5109389033
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications
2020 · R. K. Siddharth, Y. Jaya Satyanarayana, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 72
A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application
2021 · Suraj Singh Dohar, Siddharth R. K., et al. · IEEE Transactions on Electron Devices · 44
Random Forest Regression Analysis for Estimating Dielectric Properties in Epoxy Composites Doped with Hybrid Nano Fillers
2024 · Bansi Shingala, Piyushkumar Panchal, et al. · Journal of Macromolecular Science Part B · 43
Design of Low Power 5-Bit Hybrid Flash ADC
2016 · S.M. Mayur, R.K. Siddharth, et al. · IEEE Computer Society Annual Symposium on VLSI · 20
A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS
2023 · Suraj Singh Dohar, Siddharth R. K., et al. · IEEE Transactions on Electron Devices · 18
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing
2023 · K. G. Shreeharsha, R. K. Siddharth, et al. · IEEE Access · 13
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Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing
2017 · Sumit Khalapure, Siddharth R.K., et al. · IEEE Computer Society Annual Symposium on VLSI · 13
6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process
2020 · Siddharth Rajkumar Kala, Sushma Chandaka, et al. · IET Circuits Devices & Systems · 12
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing
2024 · K. G. Shreeharsha, R. K. Siddharth, et al. · IEEE Access · 9
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A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications
2020 · Suraj Dohar, R. K. Siddharth, et al. · IEEE Computer Society Annual Symposium on VLSI · 8
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC
2017 · Mayur S.M., Siddharth R.K., et al. · IEEE Computer Society Annual Symposium on VLSI · 8
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications
2021 · Sanmitra Bharat Naik, R. K. Siddharth, et al. · International Conference on VLSI Design · 7
An exponential variation based PSO for analog circuit sizing in constrained environment
2024 · Shreeharsha K.G., Siddharth R.K., et al. · AEU - International Journal of Electronics and Communications · 6
N-Parallel Paths-Based D-Latch for High-Speed Applications
2024 · R. Rakhi, R. K. Siddharth, et al. · IEEE Access · 6
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS
2023 · Rathod Balaji, R.K. Siddharth, et al. · IEEE International Symposium on Circuits and Systems proceedings · 5
Process Corner Calibration for Standard Cell Based Flash ADC
2019 · Pradeep R., Siddharth R.K., et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 5
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications
2018 · R. K. Siddharth, Y. B. Nithin Kumar, et al. · IEEE International Symposium on Circuits and Systems proceedings · 5
Design and Implementation of Tunable Bandpass Filter for Biomedical Applications
2016 · Saurabh B. K., Siddharth R. K., et al. · IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) · 5
An Asynchronous Analog to Digital Converter for Video Camera Applications
2019 · R. Sunil, R.K. Siddharth, et al. · IEEE Computer Society Annual Symposium on VLSI · 4
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications
2018 · Siddharth R.K., Sunil R., et al. · IEEE Computer Society Annual Symposium on VLSI · 4
A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique
2025 · Sourabh Mestry, Siddharth R. K, et al. · IEEE International Symposium on Circuits and Systems proceedings · 3
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process
2023 · Rupesh D. Kadhao, Siddharth R. K., et al. · International Conference on VLSI Design · 3
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process
2021 · Peta Guruprakashkumar, Siddharth R. K., et al. · IEEE International Symposium on Circuits and Systems proceedings · 3
Two-Step Flash ADC Using Standard Cell Based Flash ADCs
2019 · Rahul E., Siddharth R.K., et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 3
Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating Techniques
2024 · Yamana Ashok Kumar, Nithin Kumar Y.B, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 2
Works count: 41
Citation count: 334
H-index: 9
I10-index: 8
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