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César Pedraza
Observed names:
C. Pedraza,
Cesar Pedraza
Observed institutions:
Universidade de São Paulo,
Universidad Rey Juan Carlos,
Universidad Santo Tomás,
Universidad Santo Tomás
OpenAlex ID:
A5109954838
Cluster architecture based on low cost reconfigurable hardware
2008
·
Cesar Pedraza
, Emilio Castillo
, et al.
·
International Conference on Field Programmable Logic and Applications (FPL)
·
13
Hierarchical NoC-based security for MP-SoC dynamic protection
2012
·
Johanna Sepulveda
, Guy Gogniat
, et al.
·
IEEE Latin American Symposium on Circuits and Systems (LASCAS)
·
12
Genetic Algorithm for Boolean minimization in an FPGA cluster
2010
·
César Pedraza
, Javier Castillo
, et al.
·
The Journal of Supercomputing
·
10
3D-LeukoNoC: A dynamic NoC protection
2014
·
Johanna Sepulveda
, Guy Gogniat
, et al.
·
International Conference on ReConFigurable Computing and FPGAs (ReConFig)
·
8
Fast parallel audio fingerprinting implementation in reconfigurable hardware and GPUs
2011
·
Jose Ignacio Martinez
, Jaime Vitola
, et al.
·
Southern Conference on Programmable Logic (SPL)
·
8
Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems
2007
·
Pablo Huerta
, Javier Castillo
, et al.
·
Southern Conference on Programmable Logic (SPL)
·
8
QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs
2013
·
J. Sepulveda
, G. Gogniat
, et al.
·
IEEE Latin American Symposium on Circuits and Systems (LASCAS)
·
6
Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping
2012
·
Martha Johanna Sepúlveda
, Wang Chau
, et al.
·
Genetic and Evolutionary Computation Conference Companion (GECCO Companion)
·
4
Low Cost High Performance Reconfigurable Computing
2013
·
Javier Castillo
, Jose Luis Bosque
, et al.
·
Springer eBooks
·
2
Performance evaluation for the hash generation phase of a democratic blockchain
2020
·
Luis Lugo
, Cesar Pedraza
·
International Journal of Internet Technology and Secured Transactions
·
1
Parallel algorithm for evolvable-based boolean synthesis on GPUs
2013
·
Jaime Vitola
, Adriana Sanabria
, et al.
·
Analog Integrated Circuits and Signal Processing
·
1
Parallel algorithm for evolvable-based boolean synthesis on GPUs
2012
·
Jaime Vitola
, Adriana Sanabria
, et al.
·
IEEE Latin American Symposium on Circuits and Systems (LASCAS)
·
1
Cartesian genetic algorithm for boolean synthesis with power consumption restriction
2014
·
Jaime Vitola
, Cesar Pedraza
, et al.
·
IEEE Colombian Workshop on Circuits and Systems (CWCAS)
Síntesis booleana con programación genética paralela en CPU y GPU
2013
·
Cesar Pedraza
, Jaime Oyaga
, et al.
·
Ingenium Revista de la facultad de ingeniería
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Works count:
15
Citation count:
74
H-index:
6
I10-index:
3
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