Get started
Author

Sergei Sawitzki

Observed names: S. Sawitzki, Sawitzki, Sergei
OpenAlex ID: A5110272995
Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
2009 · Irfan Habib, Özgün Paker, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 38
Multistandard FEC Decoders for Wireless Devices
2008 · J. Dielissen, Nur Engin, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 19
Power-efficient application-specific VLIW processor for turbo decoding
2002 · M. Bekooij, J. Dielissen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 16
Scalable reconfigurable channel decoder architecture for future wireless handsets
2007 · Krishnaiah Gummidipudi, N. Engin, et al. · 12
High-Throughput and Low-Power Architectures for Reed Solomon Decoder
2006 · A. Kumar, S. Sawitzki · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 12
Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets
2007 · Gummidipudi Krishnaiah, Nur Engin, et al. · Design, Automation, and Test in Europe · 9
A novel toolset for the development of fpga-like reconfigurable logic
2005 · A. Danilin, M. Bennebroek, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 9
Astra: An Advanced Space-Time Reconfigurable Architecture
2006 · Alexander Danilin, Martijn Bennebroek, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 6
High Throughput and Low Power Reed Solomon Decoder for Ultra Wide Band
2006 · Akash Kumar, Sergei Sawitzki · Springer eBooks · 5
High Throughput Reed Solomon Decoder for Ultra Wide Band
2004 · Akash Kumar, Sergei Sawitzki · 4
Improving code efficiency for reconfigurable VLIW processors
2002 · S. Kohler, J. Braunes, et al. · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · 4
A conceptual toolchain for an application domain specific reconfigurable logic architecture
2014 · Timm Bostelmann, Sergei Sawitzki · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 2
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL
2011 · Stefan Schulze, Sergei Sawitzki · Lecture notes in computer science · 2
Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs
2004 · Alexander Danilin, Sergei Sawitzki · Lecture notes in computer science · 2
Towards a guided design flow for heterogeneous reconfigurable architectures
2015 · Timm Bostelmann, Sergei Sawitzki · International Conference on Field Programmable Logic and Applications (FPL) · 1
Improving FPGA placement with a self-organizing map
2013 · Timm Bostelmann, Sergei Sawitzki · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 1
Processor design using a functional hardware description language
2012 · S. Schulze, S. Sawitzki · Microprocessors and Microsystems · 1
Mapping a VLIW×SIMD Processor on an FPGA: Scalability and Performance
2007 · Micha Nelissen, Kees van Berkel, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 1
Formal verification for microprocessors with extendable instruction set
2002 · S. Sawitzki, R.G. Spallek, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 1
Improving the Gradient Descent Based FPGA-Placement Algorithm
2020 · Tobias Thiemann, Timm Bostelmann, et al.
FPGA-basierter Protein- und DNA-Sequenzvergleich zur optimierten Datenbanksuche mit dem BLAST-Algorithmus
2017 · Starke, Thomas Fabian, Bostelmann, Timm, et al. · Gesellschaft für Informatik (GI)
A Heterogeneous Architecture Template for Application Domain Specific Reconfigurable Logic
2015 · Timm Bostelmann, Sergei Sawitzki · Austrochip Workshop on Microelectronics (Austrochip)
Technical demonstrations session
2014 · Shanyuan Gao, John Watson, et al. · International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Chapter 12 FEC Decoders for Future Wireless Devices: Scalability Issues and Multi-standard Capabilities
2009 · J. Dielissen, N. Engin, et al. · TU/e Research Portal
FEC Decoders for FutureWireless Devices: Scalability Issues and Multi-standard Capabilities
2009 · John Dielissen, Nur Engin, et al. · Integrated circuits and systems
Works count: 31
Citation count: 145
H-index: 7
I10-index: 5
Year
Topic
Type