Author

D.Yu. Stepchenkov

Observed names: D. Y. Stepchenkov, D. Yu. Stepchenkov, D.Y. Stepchenkov, Dmitri Stepchenkov, Dmitri Y. Stepchenkov, Д.Ю. Степченков, Дмитрий Юрьевич Степченков

Institutions: Russian Academy of Sciences, Institute of Informatics Problems, Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences

Observed institutions: Russian Academy of Sciences, Institute of Informatics Problems, Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences

OpenAlex ID: A5110417664

Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation

2010 · Yuri Stepchenkov, Yuri Diachenko, et al. · Lecture notes in computer science · 8

Speed-independent fused multiply add and subtract unit

2016 · Yuri Stepchenkov, Victor Zakharov, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 7

Speed-independent floating point coprocessor

2015 · Y. A. Stepchenkov, V. N. Zakharov, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 6

Hardware verification of the recurrent signal processor on FPGA

2021 · Yu.G. Diachenko, Yu.A. Stepchenkov, et al. · Problems of advanced micro- and nanoelectronic systems development · 2

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Self-Timed Trigger Synthesis with Composite Write-Enable Input

2024 · Yuri A. Stepchenkov, Yuri G. Diachenko, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 1

Self-Timed Storage Register Cases

2022 · Yuri G. Diachenko, Yuri I. Shikunov, et al. · International Siberian workshops and tutorials on electron devices and materials · 1

Hardening Self-Timed Circuit Indication against Soft Errors

2020 · Yu.A. Stepchenkov, Yu.G. Diachenko, et al. · Problems of advanced micro- and nanoelectronic systems development · 1

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Self-Timed Multiplier Performance Improvement Technique

2020 · Yu.V. Rozhdestvenskij, Yu.A. Stepchenkov, et al. · Problems of advanced micro- and nanoelectronic systems development · 1

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Delay-Insensitive Floating Point Multiply-Add-Subtract Unit

2019 · I.A. Sokolov, Y.V. Rogdestvenski, et al. · Problems of advanced micro- and nanoelectronic systems development · 1

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Delay-Insensitive Floating Point Multiply-Add-Subtract Unit

2018 · I.A. Sokolov, Yu.V. Rozhdestvenskij, et al. · Problems of advanced micro- and nanoelectronic systems development · 1

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Cell library for speed-independent VLSI

2015 · Y. A. Stepchenkov, V. N. Zakharov, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 1

Self-Timed Computing Device for High-Reliable Applications

2010 · Yu.A. Stepchenkov, Yuri Diachenko, et al. · 1

Shift Register Implementation in Self-Timed Circuits

2026 · Yuri Stepchenkov, Yuri Diachenko, et al. · International Russian Smart Industry Conference (SmartIndustryCon)

Self-Timed Multiply-Add-Subtract Unit Cases

2025 · Yuri Stepchenkov, Yuri Diachenko, et al. · International Scientific-Technical Conference on Actual Problems of Electronic Instrument Engineering (APEIE)

Self-Timed Circuit Initialization

2025 · Yuri Stepchenkov, Yuri Diachenko, et al. · International Russian Automation Conference (RusAutoCon)

Self-timed shift register implementation according to synchronous counterpart Verilog-description

2025 · Yu.A. Stepchenkov, Yu.G. Diachenko, et al. · Highly available systems

Hardware Implementation of the Digital Signal Processing Algorithms in Recurrent Signal Processor on FPGA

2023 · Yu. A. Stepchenkov, N. V. Morozov, et al. · Russian Microelectronics

Реализация Синтеза Самосинхронных Схем В Базисе Бмк

2022 · Л.П. Плеханов, А.Н. Денисов, et al. · Nanoindustry Russia

Реализация Синтеза Самосинхронных Схем В Базисе Бмк

2021 · Л.П. Плеханов, А.Н. Денисов, et al. · Nanoindustry Russia

Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance

2021 · Yu.G. Diachenko, Yu.A. Stepchenkov, et al. · Problems of advanced micro- and nanoelectronic systems development