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M. Miranda
Observed name:
M Miranda
Institution:
IMEC
Observed institutions:
Fermi National Accelerator Laboratory,
IMEC,
KTH Royal Institute of Technology
ORCID:
0000-0002-6582-7709
Observed ORCID:
0000-0002-6582-7709
OpenAlex ID:
A5110792333
Memory addressing organization for stream-based reconfigurable computing
2003
·
M. Herz
, R. Hartenstein
, et al.
·
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
·
31
Variability aware modeling for yield enhancement of SRAM and logic
2011
·
M Miranda
, P Zuber
, et al.
·
Design, Automation, and Test in Europe
·
17
Matisse: a system-on-chip design methodology emphasizing dynamic memory management
2002
·
D. Verkest
, J. Leao da Silva
, et al.
·
IEEE Computer Society Annual Symposium on VLSI
·
12
System-level process variability compensation on memory organizations of dynamic applications: a case study
2006
·
C. Sanz
, M. Prieto
, et al.
·
International Symposium on Quality Electronic Design (ISQED)
·
11
Exploiting data transfer locality in memory mapping
1999
·
P. Ellervee
, M. Miranda
, et al.
·
EUROMICRO Conference
·
11
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder
2002
·
M. Palkovic
, M. Miranda
, et al.
·
10
Memory communication network exploration for low-power distributed memory organisations
2004
·
A. Papanikolaou
, K. Koppenberger
, et al.
·
SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems
·
9
Architectural exploration and optimization for counter based hardware address generation
1997
·
M. Miranda
, Mathias Kaspar
, et al.
·
9
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement
2005
·
Hua Wang
, A. Papanikolaou
, et al.
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
·
8
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor
2003
·
Pieter Op De Beeck
, C. Ghezt
, et al.
·
7
Analysis of high-level address code transformations for programmable processors
2002
·
S. Gupta
, M. Miranda
, et al.
·
Design, Automation, and Test in Europe
·
7
Architectural and Physical Design Optimizations for Efficient Intra-tile Communication
2005
·
A. Papanikolaou
, F. Starzer
, et al.
·
International Symposium on System-on-Chip
·
6
Architectural exploration and optimization for counter based hardware address generation
2002
·
M. Miranda
, M. Kaspar
, et al.
·
European Design and Test Conference
·
6
Technology aware design and design aware technology
2005
·
K. Maex
, M. Stucchi
, et al.
·
IEEE International Conference on IC Design and Technology (ICICDT)
·
5
Systematic power-performance trade-off in MPEG-4 by means of selective function inlining steered by address optimisation opportunities
2002
·
M. Palkovic
, M. Miranda
, et al.
·
4
ACP/R3000 processors in data acquisition systems
1989
·
J. Deppe
, H. Areti
, et al.
·
IEEE Transactions on Nuclear Science
·
3
Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer
2002
·
J. Leao da Silva
, Chantal Ykman-Couvreur
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
·
1
Session details: Variability aware low power design
2010
·
M. Miranda
, Tohru Ishihara
Interconnect and Architecture Planning: Global interconnect trade-off for technology over memory modules to application level: case study.
2003
·
Apostolos Papanikolaou
, M. Miranda
, et al.
·
TU/e Research Portal
Global interconnect trade-off for technology over memory modules to application level
2003
·
A. Papanikolaou
, M. Miranda
, et al.
·
International Workshop on System Level Interconnect Prediction (SLIP)
Interconnect exploration for future wire dominated technologies
2002
·
A. Papanikolaou
, M. Miranda
, et al.
·
International Workshop on System Level Interconnect Prediction (SLIP)
Interconnect exploration for future wire dominated technologies
2002
·
A. Papanikolaou
, M. Miranda
, et al.
·
International Workshop on System Level Interconnect Prediction (SLIP)
RISC Architecture Microprocessor Farm for offline analysis.
1992
·
De Barros C
, Mateus Mendes
, et al.
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Works count:
23
Citation count:
157
H-index:
8
I10-index:
6
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