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Rémi Franiatte

System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
2021 · Arnaud Garnier, Laetitia Castagne, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 22
Self-Assembly Process for 3D Die-to-Wafer using Direct Bonding: A Step Forward Toward Process Automatisation
2019 · Jouve Amandine, Loic Sanchez, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 11
Die-to-Wafer 3D Interconnections Operating at Sub-Kelvin Temperatures for Quantum Computation
2020 · Candice Thomas, Jean Charbonnier, et al. · Electronic System-Integration Technology Conference (ESTC) · 9
(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems
2022 · Perceval Coudrain, Arnaud Garnier, et al. · ECS Transactions · 4
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DC/DC converter 3D assembly for autonomous sensor nodes
2010 · Thierry Hilt, Herve Boutry, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 4
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Reliability Characterization of Ni-based Microinsert Interconnections for Flip Chip Die on Wafer Attachment and Their Evaluation in Multichip SIMCARD Prototype
2008 · Herve Boutry, Jean-Charles Souriau, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 4
3D via belt technology
2009 · Jean Brun, Herve Boutry, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 3
Through Mold Interconnection assessment for advanced Fan Out Wafer Level Packaging applications
2020 · Aurelia Plihon, Edouard Deschaseaux, et al. · Electronic System-Integration Technology Conference (ESTC) · 2
Flexible Fan-Out Wafer Level Packaging of Ultra-Thin Dies
2020 · Jean-Charles Souriau, Laetitia Castagne, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 2
A 3.19pJ/b Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-to-6 Wavelength-Flexible Link Capacity for Photonic Interposers
2026 · Yvain Thonnart, Christian Bernard, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 1
Characterization of Chip-to-Wafer Interconnects with Thick Gold Finish for Fan-Out Wafer-Level Packaging RDL-First Integration
2025 · Arnaud Garnier, Laetitia Castagné, et al. · European Microelectronics and Packaging Conference · 1
3D Superconducting interconnections
2025 · Jean-Philippe Michel, Jean Charbonnier, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 1
Reconfigurable Flexible Haptic Interface Using Localized Friction Modulation
2025 · Romain Le Magueresse, Fabrice Casset, et al. · IEEE Transactions on Haptics · 1
Packaging of a 25-Tiles Device on Large Dimension AlN Ceramic Substrate Keeping Low Dead Areas and Tight Planarity
2023 · Sarah Renault, Frédéric Berger, et al. · IEEE CPMT Symposium Japan (ICSJ) · 1
(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems
2022 · Perceval Coudrain, Arnaud Garnier, et al. · ECS Meeting Abstracts · 1
Reliability of die to wafer bonding using copper-tin interconnections
2013 · Arnaud Garnier, Rémi Franiatte, et al. · Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) · 1
Radar System-in-Package with Integrated Antennas based on Fan-Out Wafer-Level Packaging RDL-First Integration
2026 · Arnaud Garnier, Laetitia Castagné, et al. · IEEE Electronic Components and Technology Conference (ECTC)
Finite Element Modeling and Experimental Validation of Dual-Mode Ultrasonic Haptics on OLED Screens
2026 · Théotime Goubault, Fabrice Casset, et al. · International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)
Flexible hybrid electronics including a micromachined ultrasonic transducer for wearable physiological monitoring
2026 · Jean-Charles Souriau, Hélène Lhermet, et al. · SSRN Electronic Journal
Characterization and Modeling of the 3D Integration Effects on GaN-on-Si-Based HEMTs for mmW Applications
2025 · Mohammed Medbouhi, Gustavo Palomino-Marcelo, et al. · European Microwave Integrated Circuits Conference
Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration
2025 · Perceval Coudrain, Laetitia Castagné, et al. · European Microelectronics and Packaging Conference
Development of Advanced Screen-Printing Technology for Flip-Chip Transfer of Electronic Components
2025 · David Henry, Daniel Mermin, et al. · European Microelectronics and Packaging Conference
Mid-air haptic interface using a hybrid PMUT array
2024 · Casset, Fabrice, Rascle, Angelique, et al. · HAL
Development and Characterizations of Fine Pitch Flip-Chip Interconnection Using Silver Sintering
2024 · Julie Gougeon, Jean-Charles Souriau, et al. · IMAPSource Proceedings
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Development and Characterizations of Fine Pitch Flip-Chip Interconnection Using Silver Sintering
2023 · Julie Gougeon, Céline Feautrier, et al. · European Microelectronics and Packaging Conference
Works count: 32
Citation count: 68
H-index: 4
I10-index: 2
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