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S. Masui

Observed name: S. MASUI
Institution: Fujitsu (Japan)
OpenAlex ID: A5111440651
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
1993 · D.K. Su, M.J. Loinaz, et al. · IEEE Journal of Solid-State Circuits · 587
Rapid simulation of substrate coupling effects in mixed-mode ICs
2002 · N. Verghese, D.J. Allstot, et al. · Custom Integrated Circuits Conference · 101
A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology
2006 · H. Nakamoto, D. Yamazaki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 75
An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V
2002 · K. Sawada, Y. Sugawara, et al. · Symposium on VLSI Circuits · 57
Simulation of substrate coupling in mixed-signal MOS circuits
2003 · S. Masui · Symposium on VLSI Circuits · 55
An area-efficient universal cryptography processor for smart cards
2006 · Y. Eslami, A. Sheikholeslami, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 53
A 13.56 MHz CMOS RF identification transponder integrated circuit with a dedicated CPU
2003 · S. Masui, E. Ishii, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 52
A ferroelectric memory-based secure dynamically programmable gate array
2003 · S. Masui, T. Ninomiya, et al. · IEEE Journal of Solid-State Circuits · 35
Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall
2004 · S. Masui, W. Yokozeki, et al. · Custom Integrated Circuits Conference · 29
A 13.56 MHz CMOS RF identification transponder integrated circuit with a dedicated CPU
1999 · S. Masui · 17
A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory
2005 · S. MASUI · IEICE Transactions on Electronics · 15
Radio channel characterization for 400 MHz implanted devices
2014 · H. W. Pflug, H. J. Visser, et al. · IEEE Wireless Communications and Networking Conference · 11
Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm
2004 · K. Mukaida, M. Takenaka, et al. · Symposium on VLSI Circuits · 11
A voltage-dependent switching-time (VDST) model of ferroelectric capacitors for low-voltage FeRAM circuits
2004 · J. Chow, A. Sheikholeslami, et al. · Symposium on VLSI Circuits · 9
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)
2004 · Y. Eslami, A. Sheikholeslami, et al. · IEEE Journal of Solid-State Circuits · 8
An adaptive reference generation scheme for 1T1C FeRAMs
2004 · T. Chandler, A. Sheikholeslami, et al. · Symposium on VLSI Circuits · 8
Ferroelectric memory based secure dynamically programmable gate array
2003 · S. Masui, T. Ninomiya, et al. · Symposium on VLSI Circuits · 8
A differential-capacitance read scheme for FeRAMs
2003 · Y. Eslami, A. Sheikholeslami, et al. · Symposium on VLSI Circuits · 6
Design and Optimization of Program and Restore Operations in CMOS-Compatible Nonvolatile Latch
2011 · J. G. Lee, S. Masui · International Conference on Solid State Devices and Materials (SSDM) · 4
gm/ID Lookup Table Based Operational Transconductance Amplifier Design Featuring Settling Time Optimization
2010 · T. Kashimura, T. Konishi, et al. · International Conference on Solid State Devices and Materials (SSDM) · 4
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm
2005 · S. MASUI · IEICE Transactions on Electronics · 1
Emerging Non-Volatile Memories
2004 · H. McAdams, T. Kawahara, et al. · 1
An analysis of threshold voltage variation in thin-film SOI MOSFETs
2002 · S. Masui, M. Tachimori · IEEE International SOI Conference (SOI) · 1
Evaluation of fixed oxide charge and oxide-silicon interface trap densities in low-dose and high-dose SIMOX wafers
2002 · S. Masui, T. Nakajima, et al. · IEEE International SOI Conference (SOI) · 1
An analysis of buried-oxide growth in low-dose SIMOX wafers by high-temperature thermal oxidation
2002 · S. Masui, K. Kawamura, et al. · IEEE International SOI Conference (SOI) · 1
Works count: 28
Citation count: 1,150
H-index: 11
I10-index: 13
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