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S. Mutoh

Observed names: Mutoh, Shin'ichiro, Mutoh, Shinichiro, S.-I. Mutoh, Shin'ichiro MUTOH, Shin'ichiro Mutoh, Shin-ichiro Mutoh, Shinichiro Mutoh, Shin‐Ichiro Mutoh, Shin’ichiro Mutoh
Institution: NTT (Japan)
OpenAlex ID: A5111523384
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
1995 · S. Mutoh, T. Douseki, et al. · IEEE Journal of Solid-State Circuits · 1,124
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
1997 · S. Shigematsu, S. Mutoh, et al. · IEEE Journal of Solid-State Circuits · 248
A 1-V high-speed MTCMOS circuit scheme for power-down applications
2002 · S. Shigematsu, S. Mutoh, et al. · Symposium on VLSI Circuits · 75
A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application
2002 · S. Mutoh, S. Shigematsu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 73
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application
1996 · S. Mutoh, S. Shigematsu, et al. · IEEE Journal of Solid-State Circuits · 69
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution
2011 · Hiroshi Makino, Shunji Nakata, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 59
1V high-speed digital circuit technology with 0.5μm multi-threshold CMOS
2002 · S. Mutoh, T. Douseki, et al. · Annual IEEE International ASIC Conference and Exhibit · 57
Design method of MTCMOS power switch for low-voltage high-speed LSIs
1999 · S. Mutoh, S. Shigematsu, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 55
Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications
2010 · Toshishige Shimamura, Mamoru Ugajin, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 28
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit
2010 · Shunji Nakata, Hirotsugu Suzuki, et al. · IEEE International Symposium on Circuits and Systems proceedings · 24
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology
2012 · Shunji Nakata, Ryota Honda, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 15
1-V, 30-MHz memory-macrocell-circuit technology with a 0.5-μm multi-threshold CMOS
2002 · S. Date, N. Shibata, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 14
A mirror metaphor interaction system: touching remote real objects in an augmented reality environment
2003 · Eiichi Hosoya, Miki Kitabata, et al. · 12
A 1V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application
1996 · S. Mutoh · 12
Static‐noise margin analysis for a scaled‐down CMOS memory cell
1992 · Takakuni Douseki, Shin‐Ichiro Mutoh · Electronics and Communications in Japan (Part II Electronics) · 11
A millimeter-sized electret-energy-harvester with microfabricated horizontal arrays and vertical protrusions for power generation enhancement
2011 · K. Ono, N. Sato, et al. · International Conference on Solid-State Sensors, Actuators and Microsystems · 9
Energy harvesting by MEMS vibrational devices with electrets
2009 · N. Sato, K. Ono, et al. · International Conference on Solid-State Sensors, Actuators and Microsystems · 9
Power management technique for 1-V LSIs using embedded processor
2002 · S. Shigematsu, S. Mutoh, et al. · Custom Integrated Circuits Conference · 9
Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading
2011 · Shunji Nakata, Hirotsugu Suzuki, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 7
Simultaneous enlargement of SRAM read/write noise margin by controlling virtual ground lines
2010 · Hiroshi Makino, Takahito Kusumoto, et al. · IEEE Interregional NEWCAS Conference (NEWCAS) · 7
Integrated CMOS-MEMS technology and its applications
2008 · Hiroki Morimura, Shinichiro Mutoh, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 7
Accelerated evaluation method for the SRAM cell write margin using word line voltage shift
2011 · Hiroshi Makino, Shunji Nakata, et al. · International Symposium on Integrated Circuits · 6
MEMS-switch-based power management with zero-power voltage monitoring for energy accumulation architecture on dust-size wireless sensor nodes
2011 · Toshishige Shimamura, Mamoru Ugajin, et al. · Symposium on VLSI Circuits · 6
Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-.MU.m CMOS for Dust-Size Sensor Nodes
2011 · Mamoru UGAJIN, Toshishige SHIMAMURA, et al. · IEICE Transactions on Electronics · 5
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation
2010 · Shunji Nakata, Shin'ichiro Mutoh, et al. · IEICE Electronics Express · 5
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Works count: 54
Citation count: 1,989
H-index: 12
I10-index: 15
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