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F.T. Liou

Observed names: F-T. Liou, F. -T. Liou, F. Liou, F. T. Liou, F.-T. Liou, F.T Liou, F.‐T. LIOU, Fou-Tai Liou
Observed institutions: Motorola (United States), Intel (United States), National Yang Ming Chiao Tung University, Brookhaven National Laboratory, United Microelectronics (Taiwan), United Microelectronics (United States)
OpenAlex ID: A5111775639
A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12∼16 A) gate oxide
2003 · S.S. Chung, S.-J. Chen, et al. · Symposium on VLSI Technology · 17
Planarized aluminum metallization for sub-0.5 mu m CMOS technology
2002 · F.S. Chen, Y.S. Lin, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 14
Hole current in dual dielectric under positive gate voltage
1983 · L.D. Yau, F.T. Liou, et al. · IEEE Electron Device Letters · 14
Reactively sputtered titanium nitride films for submicron contact barrier metallization
1993 · G. A. Dixit, C. C. Wei, et al. · Applied Physics Letters · 13
Polycrystalline In2O3 and In2O3/Y2O3 photoanodes
1983 · F. -T. Liou, C. Y. Yang, et al. · Journal of Applied Electrochemistry · 11
A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology
1986 · L.C. Parrillo, S.J. Cosentino, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
Observation of two types of trapping centers in thin film transistors using charge pumping technique
1995 · A. Balasinski, J. Worley, et al. · IEEE Electron Device Letters · 9
The prevention of charge damage on thin gate oxide from high density plasma deposition
2003 · H.H. Shih, C.Y. Tsai, et al. · International Symposium on Plasma Process-Induced Damage · 8
Identification of Si / SiO2 Interface Properties in Thin Film Transistors with Charge Pumping Technique
1995 · A. Balasinski, J. Worley, et al. · Journal of The Electrochemical Society · 8
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A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array
1989 · F.-T. Liou, Y.-P. Han, et al. · IEEE Journal of Solid-State Circuits · 5
Transmission electron microscopy characterization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process
1992 · G. A. Dixit, R. L. Hodges, et al. · Applied Physics Letters · 4
Characterization of TiN Diffusion Barrier for Submicron Technology
1992 · G. A. Dixit, F. S. Chen, et al. · MRS Proceedings · 3
Reference voltages and their stress-induced changes in thin film transistors as determined by charge pumping
2002 · A. Balasinski, J. Worley, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Wafer level reliability assessment of stress-induced voiding
2002 · H.H. Hoang, R.B. MacNaughton, et al. · International IEEE VLSI Multilevel Interconnection Conference · 1
Reliability study of planarized aluminum metallization
2002 · H.H. Hoang, F.S. Chen, et al. · International IEEE VLSI Multilevel Interconnection Conference · 1
A Low Thermal Budget High Performance 0.25–0.18 µm Merged Logic Device and Dynamic Random Access Memory Application
2000 · Wen-Kuan Yeh, Yung-Chang Lin, et al. · Japanese Journal of Applied Physics · 1
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Solid electrochemical modification of semiconductors
1982 · C.Y. Yang, F-T. Liou, et al. · Solid State Communications · 1
A 0.8 mu m CMOS technology for high performance ASIC memory and channelless gate array
2003 · F.T. Liou, Y.P. Han, et al. · Custom Integrated Circuits Conference
A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process
2002 · R. Sundaresan, C.C. Wei, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
Al-plug stacked contact/via process for deep submicron CMOS multilayer metal technology
2002 · F.T. Liou, F.S. Chen, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
High performance 0.1 μm partially depleted SOI CMOSFET
2002 · W.K. Yeh, Chiutsung Huang, et al. · IEEE International SOI Conference (SOI)
Thermal effect of 0.1 μm partially depleted SOI CMOSFET
2001 · W.K Yeh, C Huang, et al. · Microelectronic Engineering
The Impact for Gate Oxide Scaling (32A-12A) and Power Supply for Sub-0.1 μm CMOSFETs
2000 · W. K. Yeh, C. Y. Lin, et al. · International Conference on Solid State Devices and Materials (SSDM)
A Low Thermal-Budget High-Performanced 0.25-0.18um Merged Logic and DRAM
1999 · W. K. Yeh, Y. C. Lin, et al. · International Conference on Solid State Devices and Materials (SSDM)
Characterization of defects resulting from the poly-buffered local oxidation isolation process
1992 · J. W. Staman, R. L. Hodges, et al. · Proceedings annual meeting Electron Microscopy Society of America
Works count: 32
Citation count: 122
H-index: 8
I10-index: 6
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