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Author

Shu-Chun Yang

Observed names: S. J. Yang, S.J. Yang
ORCID: 0009-0004-6496-7795
Observed ORCID: 0009-0004-6496-7795
OpenAlex ID: A5111904560
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
2020 · Mu-Shan Lin, Tze-Chiang Huang, et al. · IEEE Journal of Solid-State Circuits · 98
65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application
2004 · S.K.H. Fung, H.T. Huang, et al. · Symposium on VLSI Technology · 47
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing
2019 · Mu-Shan Lin, Tze-Chiang Huang, et al. · Symposium on VLSI Circuits · 43
A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell
2007 · Kuan-Lun Cheng, C. C. Wu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 37
A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity
2009 · Mu-Shan Lin, Chien-Chun Tsai, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 22
36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating
2025 · Mu-Shan Lin, Chien-Chun Tsai, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 15
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package
2016 · Mu-Shan Lin, Chien-Chun Tsai, et al. · IEEE Hot Chips Symposium · 12
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET
2019 · Wei-Chih Chen, Shu-Chun Yang, et al. · Symposium on VLSI Circuits · 10
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
2014 · Mu-Shan Lin, Chien-Chun Tsai, et al. · IEEE Journal of Solid-State Circuits · 10
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology
2010 · Wei-Chih Chen, Chien-Chun Tsai, et al. · Custom Integrated Circuits Conference · 8
UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies
2025 · Yu-Jie Huang, Mu-Shan Lin, et al. · Custom Integrated Circuits Conference · 3
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4
2024 · Mu-Shan Lin, Chien-Chun Tsai, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2
Works count: 12
Citation count: 307
H-index: 9
I10-index: 9
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