Get started
Author

Kwangyou Seo

Observed names: K. -I. Seo, K. Seo, K.-I. Seo, Seo, Kwangyou
OpenAlex ID: A5111918918
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
2014 · K. -I. Seo, B. Haran, et al. · Symposium on VLSI Technology · 103
Ferroelectric transistors for low-power NAND flash memory
2025 · Sijung Yoo, Taek Jung Kim, et al. · Nature · 41
Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications
2011 · H.-J. Cho, K.-I. Seo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28
Pushing the limits of NAND technology scaling with ferroelectrics
2025 · Prasanna Venkatesan, Lance Fernandes, et al. · MRS Bulletin · 19
Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
2014 · K. Cheng, S. Seo, et al. · Symposium on VLSI Technology · 17
Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next‐Generation High‐Density Storage Systems
2025 · Giuk Kim, Sangho Lee, et al. · Advanced Science · 15
PDF
Comparative Study of Channel Materials for Ferroelectric NAND Applications
2025 · Lance Fernandes, Prasanna Venkatesan, et al. · IEEE International Memory Workshop (IMW) · 9
Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs With Gate-Side Injection
2025 · Yixin Qin, Saikat Chakraborty, et al. · IEEE Transactions on Electron Devices · 7
Exploring FeFET Degradation Mechanisms: Mid-Interlayer as a Viable Solution for Stable Retention, Disturb Immunity, and Low Vth Variation
2025 · Giuk Kim, Sangho Lee, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 6
Experimental Analysis and Mathematical Modeling of Program Efficiency in Gate-Side Injection Type FeFETs Depending on the Gate Interlayer
2025 · Giuk Kim, Taeho Kim, et al. · IEEE Transactions on Electron Devices · 4
Enhancing Program Speed and Diminishing Read After Write Delay by Metal Work Function Engineering
2025 · Seokjoong Shin, Giuk Kim, et al. · IEEE Electron Device Letters · 4
Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection
2025 · Sizhe Ma, Saikat Chakraborty, et al. · IEEE International Reliability Physics Symposium proceedings · 3
Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage
2025 · Yixin Qin, Saikat Chakraborty, et al. · IEEE International Reliability Physics Symposium proceedings · 3
A Highly Reliable Ferroelectric NAND Cell with Ultra-thin IGZO Charge Trap Layer: Trap Profile Engineering for Endurance and Retention Improvement
2025 · Hyunjun Kang, Hongrae Joh, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Ultrathin-Mo-Enabled NC-NAND with Sub-3.5 nm HZO for Scalable High-MW Operation
2025 · Sangho Lee, Yongsu Kim, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Stabilized negative capacitance for near-theoretical efficiency and high reliability in charge trap flash memory
2025 · Sangho Lee, Giuk Kim, et al. · Materials Today Physics · 2
Thermal Processing Limits in Oxide-Channel Ferroelectric Field Effect Transistors
2026 · Lance Fernandes, Yu-Hsin Kuo, et al. · IEEE Electron Device Letters · 1
PDF
TiO2 nanolayer-assisted top-interface engineering for disturbance-free FeFETs: a blueprint for future van der Waals memory
2026 · Hyunjun Kang, Junhyeok Kwak, et al. · Nano Convergence · 1
PDF
Channel-Side Interlayer Engineering in Laminated Fe-FETs: Trap-Driven Optimization of Memory Window, Retention, and Disturb in Ferroelectric NAND Flash
2026 · Lance Fernandes, Minji Shon, et al. · IEEE International Reliability Physics Symposium proceedings · 1
Band Engineering of Gate Interlayer for Low-Voltage Operation and Enhanced Reliability in Gate-Injection Type FeFETs
2026 · Hoon Kim, Giuk Kim, et al. · IEEE Electron Device Letters · 1
Materials Design Principles for Large Memory Windows: Coercive Voltage Engineering in Ferroelectric– Dielectric Heterostructures
2026 · Prasanna Venkatesan, Hari Jayasankar, et al. · Advanced Electronic Materials · 1
PDF
Decoupling and Quantifying Polarization and Trap Charges in MIFIS FeNAND: Insights into Charge Dynamics and Reliability
2025 · Hongrae Joh, Hyunjun Kang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 1
A Comprehensive Modeling of Gate Stack Interlayer Engineering for Ferroelectric Vertical NAND
2025 · Minji Shon, Chinsung Park, et al. · Conference digest · 1
An In-Situ Spatial-Temporal Sequence Detector for Neuromorphic Vision Sensor Empowered by High Density Vertical NAND Storage
2025 · Zhao, Zijian, Parekh, Varun Darshana, et al. · arXiv (Cornell University) · 1
PDF
Agentic TCAD Calibration Workflow for Oxide Semiconductor Transistors
2026 · Jeong, Gyujun, Lee, Junmo, et al. · arXiv (Cornell University)
PDF
Works count: 36
Citation count: 273
H-index: 7
I10-index: 6
Year
Topic
Type