Author

E.J. Lloyd

Observed name: E. J. Lloyd

Observed institution: AT&T (United States)

OpenAlex ID: A5111943314

Self-aligned cobalt disilicide for gate and interconnection and contacts to shallow junctions

1987 · S.P. Murarka, D.B. Fraser, et al. · IEEE Transactions on Electron Devices · 54

High temperature stability of PtSi formed by reaction of metal with silicon or by cosputtering

1983 · S. P. Murarka, E. Kinsbron, et al. · Journal of Applied Physics · 46

A highly manufacturable corner rounding solution for 0.18 μm shallow trench isolation

2002 · C.P. Chang, C.S. Pai, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27

High performance 0.2 μm CMOS with 25 Å gate oxide grown on nitrogen implanted Si substrates

2002 · C.T. Liu, E.J. Lloyd, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 21

Reduced electron mobility due to nitrogen implant prior to the gate oxide growth

2000 · A. Kamgar, J.T. Clemens, et al. · IEEE Electron Device Letters · 14

Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress

1999 · C.T. Liu, F.H. Baumann, et al. · Symposium on VLSI Technology · 11

High energy ion implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology

1995 · D.C. Jacobson, A. Kamgar, et al. · Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms · 10

Multiple gate oxide thickness for 2 GHz system-on-a-chip technologies

2002 · C.T. Liu, Y. Ma, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7

Fast hot-carrier aging method of charging damage measurement

2003 · K.P. Cheung, E.J. Lloyd · International Symposium on Plasma Process-Induced Damage · 6

SALVO process for sub-50 nm low-V/sub T/ replacement gate CMOS with KrF lithography

2002 · C.-P. Chang, H.-H. Vuang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6

Enabling shallow trench isolation for 0.1 /spl mu/m technologies and beyond

1999 · C.-P. Chang, S.F. Shive, et al. · Symposium on VLSI Technology · 6

Modeling transient diffusion following high energy implantation

2002 · C.S. Rafferty, H.-J. Gossmann, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4

W-polycide dual-gate structure for sub-1/4 micron low-voltage CMOS technology

2002 · J. Bevk, G.E. Georgiou, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3

A new mode of hot carrier degradation in 0.18 μm CMOS technologies

2002 · C.T. Liu, E.J. Lloyd, et al. · Symposium on VLSI Technology · 2

A simple embedded DRAM process for 0.16-μm CMOS technologies

2002 · C.T. Liu, P.W. Diodato, et al. · Symposium on VLSI Technology

Sub-50 nm Local Channel MOSFETs by SALVO Process

2001 · C.-P. Chang, S. N. Rogers, et al. · International Conference on Solid State Devices and Materials (SSDM)

Works count: 16

Citation count: 217

H-index: 7

I10-index: 7