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Author

S. Sivakumar

Observed institution: Intel (United States)
OpenAlex ID: A5112033468
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
2007 · K. Mistry, R. Chau, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 902
A 90-nm logic technology featuring strained-silicon
2004 · S.E. Thompson, M. Armstrong, et al. · IEEE Transactions on Electron Devices · 685
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
2004 · T. Ghani, M. Armstrong, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 596
A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
2014 · S. Natarajan, M. Agostinelli, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 562
A Logic Nanotechnology Featuring Strained-Silicon
2004 · S.E. Thompson, M. Armstrong, et al. · IEEE Electron Device Letters · 525
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell
2003 · S. Thompson, N. Anand, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 255
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell
2005 · P. Bai, C. Auth, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 234
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
2009 · P. Packan, S. Akbar, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 202
A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array
2008 · S. Natarajan, M. Armstrong, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 187
A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
2002 · S. Tyagi, M. Alavi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 149
A high performance 180 nm generation logic technology
2002 · S. Yang, S. Ahmed, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 89
Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing
2015 · K. Fischer, M. Agostinelli, et al. · IEEE International Interconnect Technology Conference and IEEE Materials for Advanced Metallization Conference (IITC/MAM) · 69
A high performance 0.25 μm logic technology optimized for 1.8 V operation
2002 · M. Bohr, S.S. Ahmed, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 66
An advanced low power, high performance, strained channel 65nm technology
2005 · S. Tyagi, C. Kenyon, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 64
An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V
2002 · S. Thompson, M. Alavi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62
A novel approach to dual damascene patterning
2003 · M. Hussein, S. Sivakumar, et al. · IEEE International Interconnect Technology Conference (IITC) · 9
Lithography Challenges for 32nm Technologies and Beyond
2006 · S. Sivakumar · Technical digest - International Electron Devices Meeting/Technical digest · 8
Dual damascene patterning of polymer interlayer dielectrics
2004 · M. Hussein, R. Brain, et al. · IEEE International Interconnect Technology Conference (IITC) · 3
A 45nmLogicTechnology withHigh-k+Metal GateTransistors, Strained Silicon, 9CuInterconnect Layers, 193nmDryPatterning, and100%Pb-free Packaging
2007 · K. Mistry, C. C. Allen, et al.
Works count: 19
Citation count: 4,667
H-index: 15
I10-index: 15
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