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Hugh Mair

Observed names: H. Mair, Hugh T Mair, Mair Hugh
OpenAlex ID: A5112318399
An architecture of high-performance frequency and phase synthesis
2000 · H. Mair, Liming Xiu · IEEE Journal of Solid-State Circuits · 109
90nm low leakage SoC design techniques for wireless applications
2005 · P. Royannez, H. Mair, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 97
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V
2011 · Mahmut E. Sinangil, Hugh Mair, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 78
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques
2008 · Gordon Gammie, Alice Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 68
A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations
2007 · H. Mair, A. Wang, et al. · Symposium on VLSI Circuits · 65
A 28 nm 0.6 V Low Power DSP for Mobile Applications
2011 · N. Ickes, G. Gammie, et al. · IEEE Journal of Solid-State Circuits · 61
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors
2010 · G. Gammie, A. Wang, et al. · Proceedings of the IEEE · 37
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance
2016 · Hugh T Mair, Gordon Gammie, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 32
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver
2011 · Andrew K. Joy, Hugh Mair, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 31
A 28nm 0.6V low-power DSP for mobile applications
2011 · Gordon Gammie, Nathan Ickes, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 30
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance
2017 · Hugh Mair, Gordon Lin, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 27
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques
2015 · Hugh Mair, Gordon Gammie, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 24
A 65 nm CMOS technology for mobile and digital signal processing applications
2005 · A. Chattedee, J. Yoon, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 21
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC
2020 · Hugh Mair, Ericbill Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11
2.2 A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET
2023 · Bo-Jr Huang, Alfred Tsai, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
4.1 A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem
2021 · Hsinchen Chen, Rolf Lagerquist, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip
2006 · U. Ko, C. Raibaut, et al. · Symposium on VLSI Circuits · 9
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC
2022 · Ashish Nayak, HsinChen Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU
2024 · Chien-Yu Lu, Bo-Jr Huang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 4
8.2: Run-Time Power Management System by on-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core CPU
2025 · Chien-Yu Lu, Bo-Jr Huang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 3
2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC
2024 · Anshul Varma, Sumanth Gururajarao, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 3
Session 17 overview: SRAM
2016 · Hugh Mair, Atsushi Kawasumi · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 1
Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor
2006 · P. Royannez, H. Mair, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 1
An ASIC design flow of deep submicron succeeds on first pass
2002 · H. Mair, Liming Xiu · IEEE International Conference on Solid-State and Integrated Circuit Technology · 1
10.2 A Dynamic Performance Augmentation in a 3nm-Plus Mobile CPU
2026 · Chien-Yu Lu, Bo-Jr Huang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Works count: 42
Citation count: 739
H-index: 13
I10-index: 14
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