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Yu. A. Stepchenkov

Observed names: Stepchenkov Yuri, Y. A. Stepchenkov, Y.A. Stepchenkov, Yu. Stepchenkov, Yu.A. Stepchenkov, Yuri A. Stepchenkov, Yuri Afanasyevich Stepchenkov, Yuri Stepchenkov, Yuriy Stepchenkov, Yury A. Stepchenkov, Yury Stepchenkov, Ю А Степченков, Ю.А. Степченков
ORCID: 0000-0003-4784-7519
Observed ORCID: 0000-0003-4784-7519
OpenAlex ID: A5015068592
Improvement of the Natural Self-Timed Circuit Tolerance to Short-Term Soft Errors
2020 · Yuri Afanasyevich Stepchenkov, Anton Nikolaevich Kamenskih, et al. · Advances in Science Technology and Engineering Systems Journal · 61
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Fault-Tolerance of Self-Timed Circuits
2019 · Yuri A. Stepchenkov, Anton N. Kamenskih, et al. · International Conference on Dependable Systems, Services and Technologies (DESSERT) · 53
Fault-tolerant Selt-timed Counters
2023 · Aleksandr Zatsarinny, Yuriy Stepchenkov, et al. · International Conference on Mathematical Modeling in Materials Science of Electronic Components (MMMSEC) · 40
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Self-Timed Circuitry Retrospective
2020 · Victor Zakharov, Yury Stepchenkov, et al. · 12
Energy Efficient Speed-Independent 64-bit Fused Multiply-Add Unit
2019 · Yury Stepchenkov, Dmitry Stepchenkov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 11
Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems
2022 · I. A. Sokolov, Yu. A. Stepchenkov, et al. · Automation and Remote Control · 10
Hybrid Multi-Core Recurrent Architecture Approbation on FPGA
2019 · Yury Stepchenkov, Yury Shikunov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 8
Data redundancy problems in data-flow computing and solutions implemented on the recurrent architecture
2017 · Yury Shikunov, Yury Stepchenkov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 8
Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation
2010 · Yuri Stepchenkov, Yuri Diachenko, et al. · Lecture notes in computer science · 8
DSP Filter Kernels Preliminary Benchmarking for Recurrent Data-flow Architecture
2021 · Yury A. Stepchenkov, Dmitry V. Khilko, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 7
Increasing Self-Timed Circuit Soft Error Tolerance
2020 · Igor Sokolov, Yury Stepchenkov, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 7
Recurrent mechanism developments in the data-flow computer architecture
2018 · Yury Shikunov, Yury Stepchenkov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 7
Speed-independent fused multiply add and subtract unit
2016 · Yuri Stepchenkov, Victor Zakharov, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 7
Hardware and software modelling and testing of non-conventional data-flow architecture
2016 · Yuri Shikunov, Dmitry Khilko, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 7
Problems of analysis of semimodularity and energy-reliability of resilient self-timed circuits
2015 · A. N. Kamenskikh, Yu. A. Stepchenkov, et al. · Russian Electrical Engineering · 7
Self-Timed Multiply-add-subtract Unit Alternates
2020 · Yury A. Stepchenkov, Yury G. Diachenko, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 6
Speed-independent floating point coprocessor
2015 · Y. A. Stepchenkov, V. N. Zakharov, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 6
Advanced Indication of the Self-Timed Circuits
2019 · Yury Stepchenkov, Yury Diachenko, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 5
Self-timed Fused Multiply-add Unit Performance Improvement
2022 · Igor A. Sokolov, Yuri V. Rogdestvenski, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 4
Development of Capsule Programming Means for Recurrent Data-flow Architecture
2018 · D.V. Khilko, Yu.A. Stepchenkov, et al. · Problems of advanced micro- and nanoelectronic systems development · 4
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Mathematical Models of Critical Soft Error in Synchronous and Self-Timed Pipeline
2025 · Igor Sokolov, Yuri Stepchenkov, et al. · Mathematics · 3
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Desynchronization of a Synchronous Circuit to Synthesize Self-Timed Circuit
2024 · Dmitry V. Khilko, Yuri A. Stepchenkov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 3
Self-timed Circuits as a Basis for Developing Next Generation High-reliable High-performance Computers
2020 · Aleksandr Zatsarinny, Yuriy Stepchenkov, et al. · International Conference on Mathematical Modeling in Materials Science of Electronic Components (MMMSEC) · 3
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Self-Timed Counter Synthesis
2024 · Yuri Diachenko, Yuri Stepchenkov, et al. · International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM) · 2
Synthesis of Self-Timed Circuits with Memory
2024 · Igor Sokolov, Yuri Stepchenkov, et al. · International Russian Smart Industry Conference (SmartIndustryCon) · 2
Works count: 78
Citation count: 323
H-index: 8
I10-index: 6
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