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E. R. Hsieh

Observed names: E R Hsieh, E R. Hsieh, E Ray Hsieh, E Ray Hsieh Hsieh, E-Ray Hsieh, E. Hsieh, E. Ray Hsieh, E.R. Hsieh, E‐Ray Hsieh, Hsieh, E Ray
ORCID: 0000-0001-8457-704X
Observed ORCID: 0000-0001-8457-704X
OpenAlex ID: A5112737249
High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
2019 · E.R. Hsieh, M. Giordano, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 54
RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays
2021 · Binh Q. Le, Akash Levy, et al. · IEEE Transactions on Electron Devices · 43
Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array
2021 · E. R. Hsieh, X. Zheng, et al. · IEEE Electron Device Letters · 34
A FORMing-Free HfO2-/HfON-Based Resistive-Gate Metal–Oxide–Semiconductor Field-Effect-Transistor (RG-MOSFET) Nonvolatile Memory With 3-Bit-Per-Cell Storage Capability
2021 · E. R. Hsieh, K. T. Chen, et al. · IEEE Transactions on Electron Devices · 18
The experimental demonstration of the BTI-induced breakdown path in 28nm high-k metal gate technology CMOS devices
2014 · E. R. Hsieh, P. Y. Lu, et al. · Symposium on VLSI Technology · 17
The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found
2012 · E. R. Hsieh, Y. L. Tsai, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17
FinFET Plus: A Scalable FinFET Architecture with 3D Air-Gap and Air-Spacer Toward the 3nm Generation and Beyond
2021 · C. K. Chiang, H. Pai, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 15
An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
2018 · E Ray Hsieh, Meng-Ru Jiang, et al. · IEEE Journal of the Electron Devices Society · 15
A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
2017 · E. Ray Hsieh, Yen Chen Kuo, et al. · IEEE Transactions on Electron Devices · 15
The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors
2010 · E. R. Hsieh, Steve S. Chung · Applied Physics Letters · 15
The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown
2015 · E. R. Hsieh, Z. H. Huang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 13
The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique
2012 · H. M. Tsai, E. R. Hsieh, et al. · Symposium on VLSI Technology · 13
New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress
2011 · E. R. Hsieh, Steve S. Chung, et al. · IEEE International Reliability Physics Symposium proceedings · 13
Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM
2005 · Yung-Hsien Wu, E. Hsieh, et al. · IEEE Electron Device Letters · 12
Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)
2019 · Y. Xiao, E. R. Hsieh, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 11
A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password
2020 · W. C. Wang, C. C. Chuang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
Oxygen diffusion barrier on interfacial layer formed with remote NH3 plasma treatment
2021 · Dun-Bao Ruan, Kuei-Shu Chang-Liao, et al. · Surface and Coatings Technology · 9
Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications
2012 · C. L. Yang, C. H. Tsai, et al. · IEEE Electron Device Letters · 9
Cryogenic Quasi-Ballistic Transport Enhanced by Strained Silicon Technologies in 14-nm Complementary Fin Field Effect Transistors Through Virtual Source Model
2022 · E Ray Hsieh, Zih Ying Wang, et al. · IEEE Transactions on Electron Devices · 8
Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance
2020 · Akancha Gupta, C. K. Chiang, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 8
A novel one transistor resistance-gate nonvolatile memory
2016 · Steve S. Chung, E. R. Hsieh, et al. · Conference digest · 8
Emulator of Gene Mutation: Interfering True Random Number Generators Using Resistive-Gate Non-Volatile-Memories
2022 · E. Ray Hsieh, Po Hsiung Huang, et al. · IEEE Electron Device Letters · 7
A three-bit-per-cell via-type resistive random access memory gated metal-oxide semiconductor field-effect transistor non-volatile memory with the FORMing-free characteristic
2021 · E Ray Hsieh, Yi Xiang Huang, et al. · Semiconductor Science and Technology · 7
Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator
2020 · W. Y. Yang, B. Y. Chen, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications
2018 · H.W. Cheng, E. R. Hsieh, et al. · International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) · 7
Works count: 119
Citation count: 520
H-index: 13
I10-index: 16
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