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W.Y. Lien
Observed names:
W. Y. Lien,
W.-Y. Lien,
Wan-Ping Lien
Institution:
Micron (Taiwan)
Observed institutions:
Taiwan Semiconductor Manufacturing Company (Taiwan),
Micron (Taiwan)
OpenAlex ID:
A5113241963
A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell
2007
·
Kuan-Lun Cheng
, C. C. Wu
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
36
Pocket Implantation Effect on Drain Current Flicker Noise in Analog nMOSFET Devices
2004
·
J.-W. Wu
, C.-C. Cheng
, et al.
·
IEEE Transactions on Electron Devices
·
35
A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization
2004
·
C.H. Chen
, C.S. Chang
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
29
0.13- $muhbox m$ RF CMOS and Varactors Performance Optimization by Multiple Gate Layouts
2004
·
C.-C. Ho
, C.-W. Kuo
, et al.
·
IEEE Transactions on Electron Devices
·
25
A Ku-band CMOS low-noise amplifier
2005
·
Kuo-Liang Deng
, Ming-Da Tsai
, et al.
·
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
·
24
A robust shallow trench isolation (STI) with SiN pull-back process for advanced DRAM technology
2003
·
C.H. Li
, K.C. Tu
, et al.
·
ASMC proceedings
·
13
The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips
2004
·
D.D. Tang
, W.C. Lin
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
12
45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application
2007
·
Samuel K.H. Fung
, H.C. Lo
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
11
Low-K/Cu CMOS logic based SoC technology for 10 Gb transceiver with 115 GHz f/sub T/, 80 GHz f/sub MAX/ RF CMOS, high-Q MiM capacitor and spiral Cu inductor
2004
·
J.C. Guo
, W.Y. Lien
, et al.
·
Symposium on VLSI Technology
·
10
A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies
2003
·
W.Y. Lien
, W.G. Yeh
, et al.
·
ASMC proceedings
·
8
0.13/spl mu/m low voltage logic based RF CMOS technology with 115GHz f/sub T/ and 80GHz f/sub MAX/
2003
·
J.C. Guo
, C.H. Huang
, et al.
·
European Microwave Conference (EuMC)
·
6
A simple transmission line de-embedding method for accurate RF CMOS noise modeling
2004
·
J.C. Guo
, C.H. Huang
, et al.
·
Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium
·
3
0.13-μm low-κ-Cu CMOS logic-based technology for 2.1-gb high data rate read-channel
2004
·
Jyh Chyurn Guo
, W.Y. Lien
, et al.
·
IEEE Transactions on Electron Devices
·
2
0.13 ?m Low Voltage Logic Based RF CMOS Technology with 115GHz fT and 80GHz fMAX
2003
·
J. C. Guo
, C. H. Huang
, et al.
·
European Microwave Conference (EuMC)
·
2
A Role of N2 and O2 Gasses in Post Etch Treatment (PET) for Removing Fluorocarbon Based By-Product Outgassing in DRAM Memory
2023
·
Jeff J. Ye
, Wan-Ping Lien
, et al.
·
ASMC proceedings
·
1
Halo and LDD Engineering for Multiple VT High Performance Analog Devices in 0.13μm CMOS Technology
2004
·
J. C. Guo
, W.Y. Lien
, et al.
·
International Conference on Solid State Devices and Materials (SSDM)
Modeling of Pocket Implant Effect on Drain Current Flicker Noise in High Performance Analog CMOS Devices
2003
·
Jun-Wei Wu
, J. C. Guo
, et al.
·
International Conference on Solid State Devices and Materials (SSDM)
0.13μm Low-K/Cu Logic CMOS Based Technology for High Performance Analog Devices
2003
·
J. C. Guo
, W.Y. Lien
, et al.
·
International Conference on Solid State Devices and Materials (SSDM)
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Works count:
19
Citation count:
217
H-index:
9
I10-index:
9
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