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W.C. Chiou

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
2017 · S. Y. Hou, W. Chris Chen, et al. · IEEE Transactions on Electron Devices · 227
System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration
2019 · Ming-Fa Chen, Fang-Cheng Chen, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 186
Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2
2021 · P. K. Huang, C. Y. Lu, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 103
3D Multi-chip Integration with System on Integrated Chips (SoIC™)
2019 · C.C. Hu, M.F. Chen, et al. · Symposium on VLSI Technology · 72
High density 3D integration using CMOS foundry technologies for 28 nm node and beyond
2010 · J.C. Lin, W.C. Chiou, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 70
Ultra High Density SoIC with Sub-micron Bond Pitch
2020 · Y. H. Chen, C. A. Yang, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 69
Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration
2019 · S.Y. Hou, H. Hsia, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 64
SoIC for Low-Temperature, Multi-Layer 3D Memory Integration
2020 · M. F. Chen, C. S. Lin, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 52
Low Temperature SoIC Bonding and Stacking Technology for 12-/16-Hi High Bandwidth Memory (HBM)
2020 · M. F. Chen, C. H. Tsai, et al. · IEEE Transactions on Electron Devices · 51
Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking
2009 · D.Y. Chen, W.C. Chiou, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 47
Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon Photonics Applications in HPC
2021 · H. Hsia, C.H. Tsai, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 31
High-performance Ni3Al synthesized from composite powders
1994 · Wen-Chih Chiou, Chen-Ti Hu · Metallurgical and Materials Transactions A · 19
High-aspect ratio through silicon via (TSV) technology
2012 · H.B. Chang, H.Y. Chen, et al. · Symposium on VLSI Technology · 18
An ultra-thin interposer utilizing 3D TSV technology
2012 · W.C. Chiou, K.F. Yang, et al. · Symposium on VLSI Technology · 16
Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)
2020 · C. H. Tsai, Terry Ku, et al. · IEEE Symposium on VLSI Technology · 12
A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL
2014 · W.S. Liao, C.C. Chiang, et al. · Symposium on VLSI Technology · 12
Orthotropic stress field induced by TSV and its impact on device performance
2011 · C. C. Hsieh, H. A. Teng, et al. · IEEE International Interconnect Technology Conference (IITC) · 11
Comparison between HDP CVD and PECVD silicon nitride for advanced interconnect applications
2002 · J. Yota, M. Janani, et al. · IEEE International Interconnect Technology Conference (IITC) · 10
Yield and reliability of 3DIC technology for advanced 28nm node and beyond
2011 · K.F. Yang, Ting Wu, et al. · Symposium on VLSI Technology · 9
Next Generation TSMC-SoIC® Platform for Ultra-High Bandwidth HPC Application
2024 · Yen-Ming Chen, T. Ko, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4
Thin Die Fabrication and Applications to Wafer Level System Integration
2016 · Doug C. H. Yu, Wen-Chih Chiou, et al. · Springer eBooks · 3
An integrated air gap structure to achieve high-performance TSV interconnects for 28nm 3D-IC integration
2013 · E.B. Liao, Kai-Yu Cheng, et al. · Symposium on VLSI Technology · 3
Low k damage control & its reliability for organic hybrid dual damascene
2004 · Y.N. Su, J.H. Shieh, et al. · International Symposium on the Physical and Failure Analysis of Integrated Circuits · 3
Electrochemically induced defects during post Cu CMP cleaning
2004 · W.C. Chiou, Y.H. Chen, et al. · IEEE International Interconnect Technology Conference (IITC) · 3
Production Worthy 3D Interconnect Technology
2008 · W.C. Chiou, C.H. Yu · 2
Works count: 33
Citation count: 1,103
H-index: 14
I10-index: 18
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