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Ik-Hyeon Jeon

Observed name: Ik‐Hyeon Jeon
Observed institution: Kwangwoon University
ORCID: 0009-0001-5199-5824
Observed ORCID: 0009-0001-5199-5824
OpenAlex ID: A5114881387
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing
2025 · Ik-Hyeon Jeon, Joo-Hyung Chae · IEEE Transactions on Circuits and Systems I Regular Papers · 5
A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM
2025 · Ho-Sung Lee, Ik-Hyeon Jeon, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2
Probabilistic Computing via Gate‐Tunable Random Telegraph Noise
2026 · Gyungwon Yun, Jin Pyo Kang, et al. · Advanced Science · 1
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A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes
2024 · Hyeonjun Cheon, Ho-Sung Lee, et al. · International SoC Design Conference · 1
7T SRAM Macro Supporting 2W/2R Adjacent Dual-Row Access for Enhanced Memory Bandwidth and Energy Efficiency
2026 · Ho-Sung Lee, Ik-Hyeon Jeon, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
68.22 TOPS/W Full Boolean Logic Supportable eDRAM-Based Digital CIM with Energy-Efficient Input-Aware Toggle-Rate-Reduced Adder
2026 · Ik-Hyeon Jeon, Ho-Sung Lee, et al. · Custom Integrated Circuits Conference
URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros
2025 · Ho-Sung Lee, Ik-Hyeon Jeon, et al. · IEEE Access
Works count: 7
Citation count: 9
H-index: 2
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