Author

S. Eshwar Rao

Institution: Sarala Birla University

Observed institution: Sarala Birla University

ORCID: 0009-0003-2831-6103

Observed ORCID: 0009-0003-2831-6103

OpenAlex ID: A5122168309

Maha_Astra: A Partition-Theoretic Framework for Precision Modeling in the 1nm and 0.5nm Transistor Regimes

2026 · S. Eshwar Rao · Research Square · 2

Asymptotic Timing Sign-off: A High-Order, Moment-Aware Framework for Solving the Process Variation Nightmare in Sub-5nm VLSI Design

2026 · S. Eshwar Rao · Research Square · 2

Resolving the Thermal Bottleneck in 3D-ICs: A Ramanujan-Bhabha Quantum-Thermal Framework for Next-Gen VLSI

2026 · S. Eshwar Rao · Research Square · 2

A Phenomenological Framework for Boson-Assisted Steep-Slope Switching: The SBR Concept

2026 · S. Eshwar Rao · Research Square · 2

Deterministic Atomic Assembly for sub-2nm VLSI: A Unified Field-Theoretic Reactor utilizing the Indian Quartet Paradigm

2026 · S. Eshwar Rao · Research Square

Bypassing the Memory Wall: A Unified Quantum-Ballistic Paradigm for Sub-5nm VLSI Interconnects

2026 · S. Eshwar Rao · Research Square

Quantum Statistical Singularities in Excitonic Transistors: A Mathematical Framework utilizing Ramanujan Mock Theta Functions

2026 · S. Eshwar Rao · Research Square

Explainable Machine Learning Framework for RTL Timing Prediction: Bridging the Gap Between Black-Box AI and Hardware Design

2026 · S. Eshwar Rao · Research Square

Works count: 8

Citation count: 8

H-index: 2

I10-index: