Author

Afifeh Ghaemnia

Observed name: A. Ghaemnia

Institutions: Ningbo University of Technology, NingboTech University, Zhejiang University

Observed institutions: Shahed University, Ningbo University of Technology, NingboTech University, Shahid Beheshti University, Zhejiang University

ORCID: 0009-0006-0928-4777

Observed ORCID: 0009-0006-0928-4777

OpenAlex ID: A5137827902

An ultra-low power high gain CMOS OTA for biomedical applications

2019 · Afifeh Ghaemnia, Omid Hashemipour · Analog Integrated Circuits and Signal Processing · 22

QD-PFD: Quasi Dynamic Dead-Zone/Blind-Zone Free PFD With 23 nW–38 μW for 2 MHz–5 GHz Range and 150-ns Settling Time PLL Applications

2023 · A. Ghaemnia, M. B. Ghaznavi-Ghoushchi · IEEE Transactions on Circuits & Systems II Express Briefs · 15

Fast‐Locking Frequency‐Hopping PLL Using Dual‐Edge Low‐Duty‐Cycle PFD With Cycle Slip Suppression

2026 · Afifeh Ghaemnia, Jincheng Yang, et al. · IET Circuits Devices & Systems · 1

CLT-PFD: Frequency-independent locking with constant lock-time phase frequency detector for design space exploration in high-performance PLLs

2026 · A. Ghaemnia, M.B. Ghaznavi-Ghoushchi, et al. · Integration

A Co‐Designed Implicit‐Reset Path PFD and Current Mismatch Compensated CP Enabling Sub‐0.5% Mismatch and Dead Zone‐Free for Low‐Spur PLLs

2026 · A. Ghaemnia, Jincheng Yang, et al. · International Journal of Circuit Theory and Applications

A 10MHz-4.5GHz dead-zone free implicit reset path PFD and current mismatch-compensation charge-pump for low-spur PLLs in 180nm CMOS

2026 · A. Ghaemnia, Jincheng Yang, et al. · AEU - International Journal of Electronics and Communications

A High-Speed Flip-Flop Architecture for Phase Frequency Detectors Using OPL and FTL Logic

2026 · A. Ghaemnia, G. Zhang · International Conference on Circuits, Systems and Simulation (ICCSS)

CDPL: Circuit Dual Parametric Loop-Filter, An Approach to Convert Type-II into Type-I PLL

2026 · A. Ghaemnia, M.B. Ghaznavi Ghoushchi, et al. · International Conference on Circuits, Systems and Simulation (ICCSS)

Deld-Pfd: 63% Lock-Time Reduction with Dead Zone-Free and Cycle Slip Suppression Dual-Edge Low-Duty Cycle Pfd for Frequency-Hopping Pll

2025 · Afifeh Ghaemnia, Guoqiang Zhang, et al. · SSRN Electronic Journal

Works count: 9

Citation count: 38

H-index: 2

I10-index: 2