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Author

Chia-Tung Ho

Observed names: Chia-tung Ho, Ho, Chia-Tung
ORCID: 0000-0002-6479-7552
Observed ORCID: 0000-0002-6479-7552
OpenAlex ID: A5138826246
PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM/VLM Agents for VLSI Physical Design
2026 · Li, Qiufeng, Chen, Rongqian, et al. · arXiv (Cornell University) · 7
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EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
2026 · Wu, Bing-Yue, Ho, Chia-Tung, et al. · arXiv (Cornell University) · 2
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AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
2026 · Wang, Yiting, Deng, Chenhui, et al. · arXiv (Cornell University) · 1
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PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking
2026 · Li, Qiufeng, Wang, Chengxuan, et al. · arXiv (Cornell University)
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TOPCELL: Topology Optimization of Standard Cell via LLMs
2026 · Zhan Song, Yu-Tung Liu, et al. · ACM/IEEE Design Automation Conference (DAC)
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
2026 · Ho, Chia-Tung, Yang, Haoyu, et al. · arXiv (Cornell University)
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Works count: 6
Citation count: 10
H-index: 2
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