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Ziyang Zheng
Observed name:
Zheng, Ziyang
Institutions:
Chinese University of Hong Kong,
Huawei Technologies (China)
Observed institutions:
East China University of Science and Technology,
Chinese University of Hong Kong,
Huawei Technologies (China)
ORCID:
0009-0001-6049-0457
Observed ORCID:
0009-0001-6049-0457
OpenAlex ID:
A5139706046
DeepGate3: Towards Scalable Circuit Representation Learning
2024
·
Zhengyuan Shi
, Ziyang Zheng
, et al.
·
24
PDF
DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations
2025
·
Sadaf Khan
, Zhengyuan Shi
, et al.
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
·
6
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
2026
·
Zhou, Jingyi
, Shi, Zhengyuan
, et al.
·
arXiv (Cornell University)
PDF
Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
2026
·
Jingyi Zhou
, Zhengyuan Shi
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
HMARS: A Hierarchical Multi-Agent Memory System for Long-Context Reasoning
2026
·
Li, Zeju
, Zheng, Ziyang
, et al.
·
arXiv (Cornell University)
PDF
Context Distillation as Latent Memory Management
2026
·
Zheng, Ziyang
, Li, Zeju
, et al.
·
arXiv (Cornell University)
PDF
The User Stickiness Shaping Path of Virtual Reward Mechanisms in Social Applications
2025
·
Ziyang Zheng
·
CPS Digital Library - Series of Conferences
PDF
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Works count:
9
Citation count:
29
H-index:
2
I10-index:
1
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