Get started
Author

Waldir Junior

Observed name: Junior, Waldir
Observed institution: Universidade Federal do Amazonas
OpenAlex ID: A5139327650
ESBMC-PLC+: A Unified IEC 61131-3 Formal Verification Framework as a PLCverif Successor
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University) · 1
PDF
ESBMC-PLC: Formal Verification of IEC 61131-3 Ladder Diagram Programs Using SMT-Based Model Checking
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University) · 1
PDF
ESBMC: A Survey of Its Evolution, Integration, and Future Directions in Formal Software Verification
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University) · 1
PDF
A Benchmark Suite and Ground-Truth Methodology for Formal Verification of IEC 61131-3 Ladder Diagram Programs
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University)
PDF
K-ESBMC: An Executable Formal Semantics of IEC 61131-3 Ladder Diagram for Validating Verifier Translations
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University)
PDF
Detecting Ladder Logic Bombs in IEC 61131-3 PLC Programs using ESBMC-PLC+: A Formal Verification Approach with Trigger Synthesis
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University)
PDF
ESBMC-Arduino: Closing the Deployment Gap for Formal Verification of Open-Hardware PLCs
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University)
PDF
Detecting Ladder Logic Bombs in IEC 61131-3 PLC Programs using ESBMC-PLC+ — Artifact
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · Zenodo (CERN European Organization for Nuclear Research)
ESBMC-GraphPLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking
2026 · Dantas, Pierre, Cordeiro, Lucas, et al. · arXiv (Cornell University)
PDF
Denoising Neural Models with Spectral QUEnching and Eigenvalue ZEroing (SQUEEZE)
2026 · Pierre Dantas, Waldir Junior, et al. · Research Square
PDF
Works count: 10
Citation count: 3
H-index: 1
I10-index:
Year
Topic
Type