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Ozgur Sinanoglu

Observed names: O. Sinanoglu, OZGUR SINANOGLU, Sinanoglu, Sinanoglu Ozgur, Sinanoglu, Ozgur
Observed institutions: New York University Abu Dhabi, University of Illinois Urbana-Champaign, University of California System, University of California San Diego, Kuwait University, Intel (Germany), New York University, Technical University of Munich, Texas A&M University, University of Bologna
ORCID: 0000-0003-0782-0397
Observed ORCID: 0000-0003-0782-0397
OpenAlex ID: A5059987567
Security analysis of logic obfuscation
2012 · Jeyavijayan Rajendran, Youngok Pino, et al. · ACM/IEEE Design Automation Conference (DAC) · 496
Fault Analysis-Based Logic Encryption
2013 · Jeyavijayan Rajendran, Huan Zhang, et al. · IEEE Transactions on Computers · 475
SARLock: SAT attack resistant logic locking
2016 · Muhammad Yasin, Bodhisatwa Mazumdar, et al. · IEEE International Symposium on Hardware Oriented Security and Trust (HOST) · 422
Security analysis of integrated circuit camouflaging
2013 · Jeyavijayan Rajendran, Michael Sam, et al. · ACM SIGSAC Conference on Computer and Communications Security (CCS) · 399
On Improving the Security of Logic Locking
2015 · Muhammad Yasin, Jeyavijayan JV Rajendran, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 351
Provably-Secure Logic Locking
2017 · Muhammad Yasin, Abhrajit Sengupta, et al. · ACM SIGSAC Conference on Computer and Communications Security (CCS) · 346
Removal Attacks on Logic Locking and Camouflaging Techniques
2017 · Muhammad Yasin, Bodhisatwa Mazumdar, et al. · IEEE Transactions on Emerging Topics in Computing · 262
Is Split Manufacturing Secure?
2013 · Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, et al. · Design, Automation, and Test in Europe · 179
Security analysis of Anti-SAT
2017 · Muhammad Yasin, Bodhisatwa Mazumdar, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 141
Is split manufacturing secure
2013 · Jeyavijayan Rajendran, Ozgur Sinanoglu, et al. · Design, Automation, and Test in Europe · 131
Logic encryption: A fault analysis perspective
2012 · J. Rajendran, Y. Pino, et al. · Design, Automation, and Test in Europe · 128
Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories
2013 · Sachhidh Kannan, Jeyavijayan Rajendran, et al. · IEEE Transactions on Nanotechnology · 127
Keynote: A Disquisition on Logic Locking
2019 · Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 125
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
2021 · Lilas Alrahis, Abhrajit Sengupta, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 115
Logic encryption: a fault analysis perspective
2012 · Jeyavijayan Rajendran, Youngok Pino, et al. · Design, Automation, and Test in Europe · 103
Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) – Unlocked
2019 · Fangfei Yang, Ming Tang, et al. · IEEE Transactions on Information Forensics and Security · 101
What to Lock?
2017 · Muhammad Yasin, Abhrajit Sengupta, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 100
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking
2020 · Nimisha Limaye, Emmanouil Kalligeros, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 99
Evolution of logic locking
2017 · Muhammad Yasin, Ozgur Sinanoglu · IFIP/IEEE International Conference on Very Large Scale Integration · 95
Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories
2015 · Sachhidh Kannan, Naghmeh Karimi, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 94
Regaining Trust in VLSI Design: Design-for-Trust Techniques
2014 · Jeyavijayan Rajendran, Ozgur Sinanoglu, et al. · Proceedings of the IEEE · 89
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OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking
2021 · Lilas Alrahis, Satwik Patnaik, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 88
Design and analysis of ring oscillator based Design-for-Trust technique
2011 · Jeyavijayan Rajendran, Vinayaka Jyothi, et al. · IEEE VLSI Test Symposium (VTS) · 88
CamoPerturb
2016 · Muhammad Yasin, Bodhisatwa Mazumdar, et al. · 83
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
2020 · Abhrajit Sengupta, Mohammed Nabeel, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 80
Works count: 398
Citation count: 9,054
H-index: 47
I10-index: 152
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