Source

IEEE Computer Society Annual Symposium on VLSI

Source type: conference

Fully OA: No

DOAJ: No

OpenAlex ID: S4306418593

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights

2016 · Renzo Andri, Lukas Cavigelli, et al. · IEEE Computer Society Annual Symposium on VLSI · 213

Fault tolerant algorithms for network-on-chip interconnect

2004 · M. Pirretti, G.M. Link, et al. · IEEE Computer Society Annual Symposium on VLSI · 200

NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories

2012 · Matt Poremba, Yuan Xie · IEEE Computer Society Annual Symposium on VLSI · 193

BLAS Comparison on FPGA, CPU and GPU

2010 · Srinidhi Kestur, John D. Davis, et al. · IEEE Computer Society Annual Symposium on VLSI · 165

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

2009 · Huaxi Gu, Kwai Hung Mo, et al. · IEEE Computer Society Annual Symposium on VLSI · 155

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate

2009 · Himanshu Thapliyal, Nagarajan Ranganathan · IEEE Computer Society Annual Symposium on VLSI · 146

Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing

2017 · Lei Xie, H.A. Du Nguyen, et al. · IEEE Computer Society Annual Symposium on VLSI · 126

A NoC Traffic Suite Based on Real Applications

2011 · Weichen Liu, Jiang Xu, et al. · IEEE Computer Society Annual Symposium on VLSI · 116

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection

2018 · Hadi Mardani Kamali, Kimia Zamiri Azar, et al. · IEEE Computer Society Annual Symposium on VLSI · 110

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Nano-PPUF: A Memristor-Based Security Primitive

2012 · Jeyavijayan Rajendran, Garrett S. Rose, et al. · IEEE Computer Society Annual Symposium on VLSI · 105

Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures

2011 · Matthew Morrison, Nagarajan Ranganathan · IEEE Computer Society Annual Symposium on VLSI · 105

Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges

2019 · Alberto Marchisio, Muhammad Abdullah Hanif, et al. · IEEE Computer Society Annual Symposium on VLSI · 92

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices

2014 · Alireza Shafaei, Yanzhi Wang, et al. · IEEE Computer Society Annual Symposium on VLSI · 91

DONUT: A Double Node Upset Tolerant Latch

2015 · Nikolaos Eftaxiopoulos, Nicholas Axelos, et al. · IEEE Computer Society Annual Symposium on VLSI · 89

A Hierarchical Hybrid Optical-Electronic Network-on-Chip

2010 · Kwai Hung Mo, Yaoyao Ye, et al. · IEEE Computer Society Annual Symposium on VLSI · 81

Three-dimensional integrated circuits: performance, design methodology, and CAD tools

2003 · S. Das, A. Chandrakasan, et al. · IEEE Computer Society Annual Symposium on VLSI · 78

Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers

2012 · Neil Hanley, Maire ONeill · IEEE Computer Society Annual Symposium on VLSI · 77

Optimal shielding/spacing metrics for low power design

2003 · R. Arunachalam, E. Acar, et al. · IEEE Computer Society Annual Symposium on VLSI · 76

Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications

2015 · Kaushik Roy, Anand Raghunathan · IEEE Computer Society Annual Symposium on VLSI · 72

Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware

2016 · Kaiyuan Guo, Lingzhi Sui, et al. · IEEE Computer Society Annual Symposium on VLSI · 69

Performance Evaluation for Three-Dimensional Networks-On-Chip

2007 · Brett Feero, Partha Pratim Pande · IEEE Computer Society Annual Symposium on VLSI · 69

Minimum area cost for a 30 to 70 Gbits/s AES processor

2004 · A. Hodjat, I. Verbauwhede · IEEE Computer Society Annual Symposium on VLSI · 69

A framework for security on NoC technologies

2003 · C.H. Gebotys, R.J. Gebotys · IEEE Computer Society Annual Symposium on VLSI · 68

Design of Division Circuits for Stochastic Computing

2016 · Te-Hsuan Chen, John P. Hayes · IEEE Computer Society Annual Symposium on VLSI · 64

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core

2016 · B. Naresh Kumar Reddy, M. H. Vasantha, et al. · IEEE Computer Society Annual Symposium on VLSI · 63

Works count: 2,248

Citation count: 17,790

H-index: 48

I10-index: 515

2yr mean citedness: 2.097