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IEEE Symposium on VLSI Circuits (VLSI-Circuits)

Source type: conference
Alternate names: 2007 IEEE Symposium on VLSI Circuits, 2018 IEEE Symposium on VLSI Circuits, 2020 IEEE Symposium on VLSI Circuits
Fully OA: No
DOAJ: No
OpenAlex ID: S7407087433
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories
2018 · K. Garello, F. Yasin, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 197
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The Phoenix Processor: A 30pW platform for sensor applications
2008 · Mingoo Seok, Scott Hanson, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 165
A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets
2016 · Bert Moons, Marian Verhelst · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 161
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An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment
2007 · Yasuhiro Morita, Hidehiro Fujiwara, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 154
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement
2018 · Hossein Valavi, Peter J. Ramadge, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 153
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
2007 · Leland Chang, Yutaka Nakamura, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 143
A machine-learning classifier implemented in a standard 6T SRAM array
2016 · Jintao Zhang, Zhuo Wang, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 142
Next generation micro-power systems
2008 · Anantha P. Chandrakasan, Denis C. Daly, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 138
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers
2018 · Zhe Yuan, Jinshan Yue, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 117
A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment
2008 · K. Nii, M. Yabuuchi, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 115
A 9b, 1.25ps Resolutilon Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue
2007 · Minjae Lee, Asad A. Abidi · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 113
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference
2018 · Bruce Fleischer, Sunil Shukla, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 100
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither
2016 · Ahmed M.A. Ali, Huseyin Dinc, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 91
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect
2016 · Koji Obata, Kazuo Matsukawa, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 81
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS
2018 · Shouyi Yin, Peng Ouyang, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 73
A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems
2016 · Qing Dong, Kaiyuan Yang, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 71
An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC
2008 · Matthew Z. Straayer, Michael H. Perrott · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 66
A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling
2008 · Dean Truong, Wayne Cheng, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 66
A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations
2007 · H. Mair, A. Wang, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 66
A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS
2008 · Ali Nazemi, Carl Grace, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 65
Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor
2007 · Scott Hanson, Bo Zhai, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 65
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range
2020 · Chung-Cheng Chou, Zheng-Jun Lin, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 64
A 350μW CMOS MSK transmitter and 400μW OOK super-regenerative receiver for Medical Implant Communications
2008 · Jose L. Bohorquez, Joel L. Dawson, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 64
A 70nm 16Gb 16-level-cell NAND Flash Memory
2007 · Noboru Shibata, Hiroshi Maejima, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 63
A wearable ear-EEG recording system based on dry-contact active electrodes
2016 · Xiong Zhou, Qiang Li, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 60
Works count: 553
Citation count: 9,487
H-index: 44
I10-index: 282
2yr mean citedness:
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