Work

Levo - A scalable processor with high IPC

Year: 2003

Type: article

Abstract: The Levo high IPC microarchitecture is described and evaluated. Levo employs instruction time-tags and Active Stations to ensure correct operation in a rampantly speculative and out-of-order resource flow execution model. The Tomasulo-algorithm-like broadcast buses are segmented; their lengths are constant, that is, do not increase with machine size. This helps to make Levo scalable. Known high-ILP techniques such as Disjoint Eager Execution and Minimal Control Dependencies are implemented in novel ways. Examples of basic Levo operation are given. A chip floorplan of Levo is presented, demonstrating feasibility and little cycle-time impact. Levo is simulated, characterizing its basic geometry and its performance.

Source: Journal of Media Literacy Education

Authors: Augustus K. Uht, David Morano, Alireza Khalafi, David Kaeli

Institutions: University of Rhode Island, IEEE Computer Society, Northeastern University

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W1469449

FWCI: 2.288

Cites: 39

Cited by: 9

Related to: 10