Work

Modular Synthesis of Timed Circuits Using Partial Order Reduction

Year: 2002

Type: article

Authors: Tomohiro Yoneda, Eric Mercer, Chris J. Myers

Institutions: National Institute of Informatics, Research Organization of Information and Systems, University of Utah

Language: English

Topic: Formal Methods in Verification

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W1515601916

FWCI: 1.582

Cites: 12

Cited by: 6

Related to: 10