Gate-all-around silicon nanowire MOSFETs : top-down fabrication and transport enhancement techniques
Year: 2010
Type: dissertation
Abstract: Scaling MOSFETs beyond 15 nm gate lengths is extremely challenging using a planar device architecture due to the stringent criteria required for the transistor switching.The top-down fabricated, gate-all-around architecture with a Si nanowire channel is a promising candidate for future technology generations.The gate-all-around geometry enhances the electrostatic control and hence gate length scalability.In addition, it enables use of an undoped channel, which has the potential to minimize threshold voltage variation due to reduced random dopant fluctuations.However, there is little known about carrier mobility in Si nanowire MOSFETs.Because of the different crystal surface orientations, the nanowire sidewalls are expected to influence carrier transport.In addition, sidewall roughness due to non-ideal lithography and etch processes can degrade the carrier transport.Technological performance boosters are thus required to enhance electron and hole transport.Uniaxial strain engineering and maskless hydrogen thermal annealing are investigated in this thesis to enhance carrier mobility in gate-all-around nanowire MOSFETs.Uniaxial tensile stress of about 2 GPa was incorporated for the first time into suspended Si nanowire channels by a novel lateral relaxation and suspension technique.Gate-all-around strained-Si nanowire n-MOSFETs were fabricated with nanowire widths in the range of 8 to 50 nm and 8 nm body thickness, demonstrating near ideal sub-threshold swing and an enhancement in long-channel current drive and transconductance of approximately 2X for strained-Si nanowires compared to control Si nanowires.Lowfield effective mobility of these devices was extracted using split capacitance-voltage measurements and the two-FET method.The analysis indicates electron mobility enhancement for strained-Si nanowires over their unstrained Si counterparts, as well as over planar SOI, specifically at high inversion charge densities.However, the mobility of these nanowires was shown to decrease with decreasing nanowire width, consistent with reported data on unstrained Si nanowires.A simple analytical model was developed to investigate the contribution of the sidewalls to the nanowire width dependence of the electron mobility.A new design and process technology was developed to accurately investigate the hole mobility of gate-allaround Si nanowires.A conformal high-κ/metal gate process, enabling uniform gating of the nanowire perimeter, was combined with a maskless hydrogen thermal anneal to reduce sidewall roughness scattering.Using this optimized process, long-channel devices with ideal sub-threshold swing (~60 mV/dec) and enhanced current drive were demonstrated, indicating the excellent quality of the nanowire/high-κ interface and low-roughness sidewalls.Capacitance-voltage characteristics of sub-micron-long Si nanowires were accurately measured and verified by quantum-mechanical simulations.Increased effective hole mobility with decreasing nanowire width was observed down to 12 nm for hydrogen annealed nanowires, attributed to the smooth, high-mobility non-( 100) sidewalls.First of all, I would like to express my sincere respect and deepest gratitude to my principal research supervisor, Prof. Judy L. Hoyt.During the past five years, Judy was the most influential person to me.She generously helped me in all the ups and downs I encountered in my research and student life at MIT.She patiently followed every single step of all my experiments and helped me troubleshoot the process failures and technical difficulties.I would also like to thank Prof. Dimitri Antoniadis, for all the technical support and helpful discussions on various projects.In fact, I learned so much from his extensive experience in semiconductor devices and his deep insight to the device physics.I'd also like to thank Prof. Tomás Palacios for contributing to and enhancing the quality of this thesis.The financial support by the FCRP Materials, Structures, and Devices Focus Center and IBM Ph.D. Fellowship program is acknowledged.I had a great opportunity to discuss to and get feedback from many professors and industrial directors through annual reviews and teleseminars.Over the past five years, I was honored to work and collaborate with many outstanding students, scientists and research staffs members at various universities and industries.Dr.
Author: Pouya Hashemi
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W1523759305