Year: 2013
Type: article
Abstract: We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We derive the device requirements for sub-100 fJ/cm/bit interconnects including tuning power, serialization-deserialization energy, and optical insertion losses. Using CMOS with integrated nanophotonics as an example platform, we derive the energy/bit, linear, and areal bandwidth density of optical interconnects. We also derive the targets for device performance which indicate the need for continued improvements in insertion losses (40 Gb/s), tuning power (6 channels).
Authors: S. Manipatruni, M. Lipson, I. A. Young
Institutions: Intel (United States), Cornell University
Language: English
Topic: Photonic and Optical Devices
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W1552397959