Work

A meta-interpreter for circuit-extraction

Year: 2002

Type: conference-paper

Abstract: The design of a VLSI circuit consists of a description of the circuit in terms of its components and subcomponents, at various levels of detail. To verify that the layout of a VLSI circuit conforms to its design, one needs to work backwards from the lowest-level description of the circuit and recognize the higher-level components it constitutes. This paper is concerned with the application of logic programming techniques in the formal verification of the structural correctness of the VLSI circuit layouts. In particular, we review Michael Dukes' Generalized Extraction System (1990) that compiles design descriptions into a set of extraction rules, and then study the benefits and the limitations of using a meta-interpreter approach to extraction.

Source: IEEE National Aerospace and Electronics Conference (NAECON)

DOI: 10.1109/naecon.1995.522010

Author: K. Thirunarayan

Institution: Wright State University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W1570032273

FWCI:

Cites: 3

Cited by:

Related to: 10