Work

Checking the error correction strength of arbitrary surface code logical gates

Year: 2012

Type: preprint

Abstract: Topologically quantum error corrected logical gates are complex. Chains of errors can form in space and time and diagonally in spacetime. It is highly nontrivial to determine whether a given logical gate is free of low weight combinations of errors leading to failure. We report a new tool Nestcheck capable of analyzing an arbitrary topological computation and determining the minimum number of errors required to cause failure.

Source: arXiv (Cornell University)

DOI: 10.48550/arxiv.1210.4249

Authors: Milburn, Thomas J., Fowler, Austin G.

Institutions: The University of Melbourne, Centre for Quantum Computation and Communication Technology

Language: English

Topic: Quantum Computing Algorithms and Architecture

Subfield: Artificial Intelligence

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funders: National Security Agency, U.S. Army, Intelligence Advanced Research Projects Activity, Centre of Excellence for Quantum Computation and Communication Technology, Australian Research Council, Army Research Office

Awards: G1382275741, G3622582212, G459367103, G576219634, G645532255, G7452299184

OpenAlex ID: W1627039141

Cites: 2

Cited by: 2

Related to: 20