Work

Analysis of Binary DC Source Reduced Switch 7-level Inverter

Year: 2015

Type: article

Abstract: This paper proposes a binary DC source reduced switch 7-level inverter. Binary DC source reduced switch inverter is triggered by the Unipolar PWM strategy having sinusoidal and trapezoidal reference with triangular carriers. These Pulse Width Modulating (PWM) strategies include Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Carrier Overlapping (CO). Performance factors like Total Harmonic Distortion (THD), VRMS (fundamental) and crest factor are evaluated for various modulation indices. Simulations were performed using MATLAB-SIMULINK. It is observed that UPDPWM strategy with trapezoidal reference provides output with relatively low distortion and UCOPWM strategy with trapezoidal reference provides relatively higher fundamental RMS output voltage.

Source: International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering

DOI: 10.11591/ijpeds.v6.i1.pp70-76

Authors: V. Arun, B. Shanthi, M. Arumugam

Institutions: Arunai Engineering College, Annamalai University

Language: English

Topic: Multilevel Inverters and Converters

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDGs: Affordable and clean energy, Industry, innovation and infrastructure

Open Access status: hybrid

OpenAlex ID: W1830642895

FWCI:

Cites: 12

Cited by: 3

Related to: 9