Work

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

Year: 2014

Type: article

Source: IEEE Transactions on Electron Devices

DOI: 10.1109/ted.2014.2322762

Authors: Rajat Vishnoi, M. Jagadesh Kumar

Institution: Indian Institute of Technology Delhi

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W1896020517

FWCI: 6.36

Cites: 22

Cited by: 112

Related to: 10