A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores
Year: 2010
Type: article
Abstract: Different from traditional processors, Moores Law was one of the reasons to duplicate cores, and at least until today it is the solution for safe consumption and operation of systems using millions of transistors. In terms of software, parallelism will be a tendency over the coming years. One of the challenges is to create tools for programmers who use HLL (High Level Language) producing hardware directly. These tools should use the utmost experience of the programmers and the flexibility of FPGA (Field Programmable Gate Array). The main aspect of the existing tools which directly convert HLL into hardware is dependence graphics. On the other hand, a dynamic dataflow architecture has implicit parallelism. ChipCflow is a tool to convert C directly into hardware that uses FPGA as a partial reconfiguration based on a dynamic dataflow architecture. In this paper, the relation between traditional dataflow architecture and contemporary architecture, as well as the main characteristics of the ChipCflow project will be presented.
Authors: Jorge Luiz e Silva, Joelmir José Lopes
Institution: Universidade de São Paulo
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W197043460